Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
Recommended Operating Conditions
|Symbol||Description||Condition||Minimum 8||Typical||Maximum 8||Unit|
|VCC||Core voltage power supply||Standard and low power 9||0.87||0.9||0.93||V|
|VCCP||Periphery circuitry and transceiver fabric interface power supply||Standard and low power 9||0.87||0.9||0.93||V|
|VCCPGM||Configuration pins power supply||1.8 V||1.71||1.8||1.89||V|
|VCCERAM||Embedded memory power supply||0.9 V 9||0.87||0.9||0.93||V|
|0.95 V 9||0.92||0.95||0.98||V|
|VCCBAT 11||Battery back-up power supply (For design security volatile key register)||—||1.14||—||1.89||V|
|VCCPT||Power supply for programmable power technology and I/O pre-driver||1.8 V||1.71||1.8||1.89||V|
|VCCIO||I/O buffers power supply||3.0 V (for 3 V I/O only)||2.85||3.0||3.15||V|
|2.5 V (for 3 V I/O only)||2.375||2.5||2.625||V|
|VCCA_PLL||PLL analog voltage regulator power supply||—||1.71||1.8||1.89||V|
|VREFP_ADC||Precision voltage reference for voltage sensor||—||1.2475||1.25||1.2525||V|
|VI 13 14||DC input voltage||3 V I/O||–0.3||—||3.3||V|
|TJ||Operating junction temperature||Extended||0||—||100||°C|
|tRAMP 16||Power supply ramp time||Standard POR||200 µs||—||100 ms||—|
|Fast POR||200 µs||—||4 ms||—|
8 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
9 You can operate –1 and –2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate –3 speed grade device only at 0.9 V typical value. Operating at 0.95 V results in higher core performance and higher power consumption. Refer to core performance in this datasheet for different typical values. For more information about the power consumption of different typical values, refer to the Intel® Quartus® Prime software, Power Analyzer report, and Early Power Estimator (EPE).
10 SmartVID is supported in devices with –3V speed grades only.
11 If you do not use the design security feature in Intel® Arria® 10 devices, connect VCCBAT to a 1.5-V to 1.8-V power supply. Intel® Arria® 10 power-on reset (POR) circuitry monitors VCCBAT. Intel® Arria® 10 devices do not exit POR if VCCBAT is not powered up.
12 For minimum and maximum voltage values, refer to the I/O Standard Specifications section.
13 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
14 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
15 For more details on the military requirement, refer to the Intel® Arria® 10 Military Temperature Range Support Technical Brief.
16 tramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
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