Visible to Intel only — GUID: mcn1413211765262
Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
Transceiver Performance for Intel® Arria® 10 GX/SX Devices
High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices
Transceiver Performance for Intel® Arria® 10 GT Devices
High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices
Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
DQS Logic Block Specifications
Memory Output Clock Jitter Specifications
OCT Calibration Block Specifications
HPS Reset Input Requirements
HPS Clock Performance
HPS PLL Specifications
Quad SPI Flash Timing Characteristics
SPI Timing Characteristics
SD/MMC Timing Characteristics
USB ULPI Timing Characteristics
Ethernet Media Access Controller (EMAC) Timing Characteristics
I2C Timing Characteristics
NAND Timing Characteristics
Trace Timing Characteristics
GPIO Interface
POR Specifications
JTAG Configuration Timing
FPP Configuration Timing
AS Configuration Timing
DCLK Frequency Specification in the AS Configuration Scheme
PS Configuration Timing
Initialization
Configuration Files
Minimum Configuration Time Estimation
Remote System Upgrades
User Watchdog Internal Circuitry Timing Specifications
Visible to Intel only — GUID: mcn1413211765262
Ixiasoft
Differential SSTL I/O Standards Specifications
I/O Standard | VCCIO (V) | VSWING(DC) (V) | VSWING(AC) (V) | VIX(AC) (V) | ||||||
---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.25 | VCCIO + 0.6 | 0.5 | VCCIO + 0.6 | VCCIO/2 – 0.175 | — | VCCIO/2 + 0.175 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | 32 | 2(VIH(AC) – VREF) | 2(VREF – VIL(AC)) | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 |
SSTL-135/ SSTL-135 Class I, II | 1.283 | 1.35 | 1.45 | 0.18 | 32 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | VCCIO/2 | VCCIO/2 + 0.15 |
SSTL-125/ SSTL-125 Class I, II | 1.19 | 1.25 | 1.31 | 0.18 | 32 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | VCCIO/2 | VCCIO/2 + 0.15 |
SSTL-12/ SSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.16 | 32 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VREF – 0.15 | VCCIO/2 | VREF + 0.15 |
POD12 | 1.16 | 1.2 | 1.24 | 0.16 | — | 0.3 | — | VREF – 0.08 | — | VREF + 0.08 |
32 The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC) and VIL(DC)).