Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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Differential SSTL I/O Standards Specifications

Table 17.  Differential SSTL I/O Standards Specifications for Intel® Arria® 10 Devices
I/O Standard VCCIO (V) VSWING(DC) (V) VSWING(AC) (V) VIX(AC) (V)
Min Typ Max Min Max Min Max Min Typ Max
SSTL-18 Class I, II 1.71 1.8 1.89 0.25 VCCIO + 0.6 0.5 VCCIO + 0.6 VCCIO/2 – 0.175 VCCIO/2 + 0.175
SSTL-15 Class I, II 1.425 1.5 1.575 0.2 32 2(VIH(AC) – VREF) 2(VREF – VIL(AC)) VCCIO/2 – 0.15 VCCIO/2 + 0.15
SSTL-135/ SSTL-135 
Class I, II 1.283 1.35 1.45 0.18 32 2(VIH(AC) – VREF) 2(VIL(AC) – VREF) VCCIO/2 – 0.15 VCCIO/2 VCCIO/2 + 0.15
SSTL-125/ SSTL-125 
Class I, II 1.19 1.25 1.31 0.18 32 2(VIH(AC) – VREF) 2(VIL(AC) – VREF) VCCIO/2 – 0.15 VCCIO/2 VCCIO/2 + 0.15
SSTL-12/ SSTL-12 
Class I, II 1.14 1.2 1.26 0.16 32 2(VIH(AC) – VREF) 2(VIL(AC) – VREF) VREF – 0.15 VCCIO/2 VREF + 0.15
POD12 1.16 1.2 1.24 0.16 0.3 VREF – 0.08 VREF + 0.08
32 The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC) and VIL(DC)).

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