Intel® Arria® 10 Device Datasheet

ID 683771
Date 2/14/2022
Document Table of Contents

HPS PLL Input Requirements

The HPS main PLL receives the clock signal from the HPS_CLK1 pin. For details on this pin, refer to the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines.

Table 59.  HPS PLL Input Requirements for Intel® Arria® 10 Devices
Description Min Typ Max Unit
Clock input range 10 50 MHz
Clock input jitter tolerance 2 %
Clock input duty cycle 45 50 55 %