Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

ID 683814
Date 1/14/2022
Public
Document Table of Contents

HPS Dedicated I/O Bank Pins

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 13.  HPS Dedicated I/O Bank Pins
HPS Pin Name Pin Functions Pin Description Connection Guidelines
HPS_CLK1 Input, Clock Dedicated clock input pin that drives the main PLL. This provides clocks to the MPU, L3/L4 sub-systems, debug sub-system and the Flash controllers. It can also be programmed to drive the peripherals. Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS. Refer to the valid frequency range of the clock source in the Intel® Arria® 10 Device Datasheet. Unless the hps_clk_f fuse is blown, an input clock must be present on this pin for the HPS to boot properly.
HPS_ nRST Bidirectional Warm reset to the HPS block. Active low bi-directional pin. When driven from the board, the system reset domains that allow debugging to operate are affected. Any cold HPS reset drives the HPS_nRST pin low. HPS_nRST may be driven low on a warm reset if enabled using the nrstwarmmask register in the Reset Manager. Connect this pin through a 1-kΩ pull-up resistor to VCCIO_HPS.
HPS_ nPOR Input Cold reset to the HPS block. Active low input that resets all HPS logic that can be reset. Places the HPS in a default state sufficient for the software to boot. This pin has an internal 25-kΩ pull-up resistor that is always active. Connect this pin through a 1–10-kΩ pull-up resistor to VCCIO_HPS.

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