Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
ID
683814
Date
7/23/2025
Public
1.1.1. Clock and PLL Pins
1.1.2. Dedicated Configuration/JTAG Pins
1.1.3. Optional/Dual-Purpose Configuration Pins
1.1.4. Partial Reconfiguration Pins
1.1.5. 3V Compatible I/O Pins
1.1.6. Differential I/O Pins
1.1.7. External Memory Interface and Hard Memory PHY Pins
1.1.8. Reference Pins
1.1.9. Voltage Sensor Pins
1.1.10. Supply Pins
1.1.11. Transceiver Pins
1.1.12. Notes to Arria® 10 GX and GT Pin Connection Guidelines
1.3.1. Example 1— Arria® 10 GX
1.3.2. Example 2— Arria® 10 GX
1.3.3. Example 3— Arria® 10 GX
1.3.4. Example 4— Arria® 10 GT
1.3.5. Example 5— Arria® 10 GT
1.3.6. Example 6— Arria® 10 GT
1.3.7. Example 7— Arria® 10 GT
1.3.8. Example 8— Arria® 10 SX
1.3.9. Example 9— Arria® 10 SX
1.3.10. Example 10— Arria® 10 SX
1.3.11. Example 11— Arria® 10 GX (Using the SmartVID Feature)
1.3.12. Notes to Power Supply Sharing Guidelines
1.2.2. HPS Dedicated I/O Bank Pins
Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
HPS Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
HPS_CLK1 | Input, Clock | Dedicated clock input pin that drives the main PLL. This provides clocks to the MPU, L3/L4 sub-systems, debug sub-system and the Flash controllers. It can also be programmed to drive the peripherals. | Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS. Refer to the valid frequency range of the clock source in the Arria® 10 Device Datasheet. Unless the hps_clk_f fuse is blown, an input clock must be present on this pin for the HPS to boot properly. |
HPS_nRST | Bidirectional | Warm reset to the HPS block. Active low bi-directional pin. When driven from the board, the system reset domains that allow debugging to operate are affected. Any cold HPS reset drives the HPS_nRST pin low. HPS_nRST may be driven low on a warm reset if enabled using the nrstwarmmask register in the Reset Manager. | Connect this pin through a 1-kΩ pull-up resistor to VCCIO_HPS. |
HPS_nPOR | Input | Cold reset to the HPS block. Active low input that resets all HPS logic that can be reset. Places the HPS in a default state sufficient for the software to boot. This pin has an internal 25-kΩ pull-up resistor that is always active. | Connect this pin through a 1–10-kΩ pull-up resistor to VCCIO_HPS. |