Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

ID 683814
Date 1/14/2022
Public
Document Table of Contents

Voltage Sensor Pins

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 9.  Voltage Sensor Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VREFP_ADC Input Dedicated precision analog voltage reference.

Tie VREFP_ADC to an external 1.25V accurate reference source (+/- 0.2%) for better ADC performance. Treat VREFP_ADC as an analog signal that together with the VREFN_ADC signal provides a differential 1.25V voltage. If no external reference is supplied, always connect VREFP_ADC to GND. An on-chip reference source (+/-10%) is activated by connecting this pin to GND.

VREFP_ADC must be equal to or lower than VCCA_PLL to prevent damage.

VREFN_ADC Input

Tie VREFN_ADC to the GND pin of an external 1.25V accurate reference source (+/- 0.2%) for better ADC performance. Treat VREFN_ADC as an analog signal that together with the VREFP_ADC signal provides a differential 1.25V voltage. If no external reference is supplied, always connect VREFN_ADC to GND.

VSIGP_[0,1] Input 2 pairs of analog differential inputs pins used with the voltage sensor inside the FPGA to monitor external analog voltages.

Tie these pins to GND of the voltage sensor feature if not used. For details on the usage of these pins, refer to the Power Management in Intel® Arria® 10 Devices chapter.

Do not drive VSIGP and VSIGN pins until the VCCA_PLL power rail has reached 1.62V to prevent damage.

VSIGN_[0,1] Input

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