Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

ID 683814
Date 1/14/2022
Public
Document Table of Contents

Notes to Intel® Arria® 10 SX Pin Connection Guidelines

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.

Intel® provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.

  1. These pin connection guidelines are based on the Intel® Arria® 10 SX device variant.
  2. Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
  3. Use the Intel® Arria® 10 Early Power Estimator (EPE) to determine the current requirements for VCC and other power supplies. Use the Intel® Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
  4. These supplies may share power planes across multiple Intel® Arria® 10 devices.
  5. Power pins should not share breakout vias from the BGA. Each ball on the BGA must have its own dedicated breakout via.
  6. Example 8, Example 9, Example 10, Figure 8, Figure 9, and Figure 10 illustrate the power supply sharing guidelines for the Intel® Arria® 10 SX devices.
  7. Low Noise Switching Regulator—a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800 kHz and 1 MHz and has fast transient response. The switching frequency range is not an Intel® requirement. However, Intel® does require the Line Regulation and Load Regulation meet the following specifications:
    • Line Regulation < 0.4%
    • Load Regulation < 1.2%
  8. The number of modular I/O banks on Intel® Arria® 10 devices depends on the device density. For the indexes available for a specific device, refer to the I/O Bank section in the Intel® Arria® 10 Device Handbook.
  9. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires that the AC-coupling capacitor is placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
  10. For item [#], refer to the device pin table for the pin-out mapping.
  11. The peripheral pins are programmable through pin multiplexors. Each pin may have multiple functions. The HPS dedicated I/O pin multiplexing is programmable using the HPS software. The pin mux will determine how the pins are used.
  12. Pin Mux Select 5, 6, 7, 9, 10, 11, and 12 will not assign any HPS dedicated pins to any specific function. Pin Mux Select 5, 6, 7, 9, 10, 11, and 12 are not listed in the HPS Peripheral Pins table.
  13. A warm reset event will not change the configured value of the HPS dedicated I/O Pin Mux.
  14. At cold reset, these pins will default to the GPIO and BSEL functions set.
  15. SD/MMC Power Enable pins are inverted. For details, refer to the Intel® Arria® 10 SoC Errata Sheet.
  16. Pin Mux Select 5, 6, 7, 9, 10, and 11 will not assign any HPS dedicated pins to any specific function. Pin Mux Select 5, 6, 7, 9, 10, and 11 are not listed in the Shared 3V I/O Bank Pins table.
  17. A warm reset event will not change the configured value of the HPS shared I/O Pin Mux.
  18. At cold reset, these pins will default to the GPIO function set.
  19. These pins are inverted or active-low signals.
  20. Do not drive the I/O pins externally during the power-up and power-down time to avoid excess current on the I/O pins:
    • Excess I/O pin current affects the device's lifetime and reliability.
    • Excess current on the 3V I/O pins can damage the Intel® Arria® 10 device.
    For the acceptable limits on the input current, refer to the Absolute Maximum Ratings section in the Intel® Arria® 10 Device Datasheet.

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