Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

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ID 683814
Date 7/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
1. Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines x
1.1. Arria® 10 GX and GT Pin Connection Guidelines 1.2. Arria® 10 SX Pin Connection Guidelines 1.3. Power Supply Sharing Guidelines for Arria® 10 Devices 1.4. Document Revision History for the Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
1.1. Arria® 10 GX and GT Pin Connection Guidelines x
1.1.1. Clock and PLL Pins 1.1.2. Dedicated Configuration/JTAG Pins 1.1.3. Optional/Dual-Purpose Configuration Pins 1.1.4. Partial Reconfiguration Pins 1.1.5. 3V Compatible I/O Pins 1.1.6. Differential I/O Pins 1.1.7. External Memory Interface and Hard Memory PHY Pins 1.1.8. Reference Pins 1.1.9. Voltage Sensor Pins 1.1.10. Supply Pins 1.1.11. Transceiver Pins 1.1.12. Notes to Arria® 10 GX and GT Pin Connection Guidelines
1.2. Arria® 10 SX Pin Connection Guidelines x
1.2.1. HPS Supply Pins 1.2.2. HPS Dedicated I/O Bank Pins 1.2.3. HPS Peripheral Pins 1.2.4. Shared 3V I/O Bank Pins 1.2.5. Notes to Arria® 10 SX Pin Connection Guidelines
1.3. Power Supply Sharing Guidelines for Arria® 10 Devices x
1.3.1. Example 1— Arria® 10 GX 1.3.2. Example 2— Arria® 10 GX 1.3.3. Example 3— Arria® 10 GX 1.3.4. Example 4— Arria® 10 GT 1.3.5. Example 5— Arria® 10 GT 1.3.6. Example 6— Arria® 10 GT 1.3.7. Example 7— Arria® 10 GT 1.3.8. Example 8— Arria® 10 SX 1.3.9. Example 9— Arria® 10 SX 1.3.10. Example 10— Arria® 10 SX 1.3.11. Example 11— Arria® 10 GX (Using the SmartVID Feature) 1.3.12. Notes to Power Supply Sharing Guidelines
1. Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

1.1.12. Notes to Arria® 10 GX and GT Pin Connection Guidelines

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.

Altera provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.

  1. These pin connection guidelines are created based on the Arria® 10 GX and GT device variants.
  2. Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
  3. Use the Arria® 10 Early Power Estimator (EPE) to determine the current requirements for VCC and other power supplies. Use the Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
  4. These supplies may share power planes across multiple Arria® 10 devices.
  5. Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
  6. Example 1 through Example 7 and Figure 1 through Figure 7 illustrate the power supply sharing guidelines for the Arria® 10 GX and Arria® 10 GT devices. Example 11 illustrates the power supply sharing guidelines for Arria® 10 GX device using the SmartVID feature.
  7. Low Noise Switching Regulator—defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800 kHz and 1 MHz and has fast transient response. The switching frequency range is not an Altera requirement. However, Altera does require the Line Regulation and Load Regulation meet the following specifications:
    • Line Regulation < 0.4%
    • Load Regulation < 1.2%
  8. The number of modular I/O banks on Arria® 10 devices depends on the device density. For the indexes available for a specific device, refer to the I/O Bank section in the Arria® 10 Device Handbook.
  9. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
  10. Decoupling for these pins depends on the design decoupling requirements of the specific board.
  11. Do not connect voltage above 1.8 V to the VREFB[[2][A, F,G,H,I,J,K, L], [3] [A, B,C,D,E,F,G, H]]N0 pins. For 3V I/O banks, tie unused VREF pins to GND.
  12. Do not drive the I/O pins externally during the power-up and power-down time to avoid excess current on the I/O pins:
    • Excess I/O pin current affects the device's lifetime and reliability.
    • Excess current on the 3 V I/O pins can damage the Arria® 10 device.
    For the acceptable limits on the input current, refer to the Absolute Maximum Ratings section in the Arria® 10 Device Datasheet.
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