Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

ID 683814
Date 1/14/2022
Public
Document Table of Contents

Differential I/O Pins

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 6.  Differential I/O Pins
Pin Name Pin Functions Pin Description Connection Guidelines
LVDS[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_[1:24]p , LVDS[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_[1:24]n I/O, TX/RX channel These are true LVDS receiver/transmitter channels on column I/O banks. Each I/O pair can be configured as LVDS receiver or LVDS transmitter. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. Connect unused pins as defined in the Intel® Quartus® Prime software.

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