Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

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ID 683814
Date 7/23/2025
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Document Table of Contents
Document Table of Contents x
1. Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
1. Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines x
1.1. Arria® 10 GX and GT Pin Connection Guidelines 1.2. Arria® 10 SX Pin Connection Guidelines 1.3. Power Supply Sharing Guidelines for Arria® 10 Devices 1.4. Document Revision History for the Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
1.1. Arria® 10 GX and GT Pin Connection Guidelines x
1.1.1. Clock and PLL Pins 1.1.2. Dedicated Configuration/JTAG Pins 1.1.3. Optional/Dual-Purpose Configuration Pins 1.1.4. Partial Reconfiguration Pins 1.1.5. 3V Compatible I/O Pins 1.1.6. Differential I/O Pins 1.1.7. External Memory Interface and Hard Memory PHY Pins 1.1.8. Reference Pins 1.1.9. Voltage Sensor Pins 1.1.10. Supply Pins 1.1.11. Transceiver Pins 1.1.12. Notes to Arria® 10 GX and GT Pin Connection Guidelines
1.2. Arria® 10 SX Pin Connection Guidelines x
1.2.1. HPS Supply Pins 1.2.2. HPS Dedicated I/O Bank Pins 1.2.3. HPS Peripheral Pins 1.2.4. Shared 3V I/O Bank Pins 1.2.5. Notes to Arria® 10 SX Pin Connection Guidelines
1.3. Power Supply Sharing Guidelines for Arria® 10 Devices x
1.3.1. Example 1— Arria® 10 GX 1.3.2. Example 2— Arria® 10 GX 1.3.3. Example 3— Arria® 10 GX 1.3.4. Example 4— Arria® 10 GT 1.3.5. Example 5— Arria® 10 GT 1.3.6. Example 6— Arria® 10 GT 1.3.7. Example 7— Arria® 10 GT 1.3.8. Example 8— Arria® 10 SX 1.3.9. Example 9— Arria® 10 SX 1.3.10. Example 10— Arria® 10 SX 1.3.11. Example 11— Arria® 10 GX (Using the SmartVID Feature) 1.3.12. Notes to Power Supply Sharing Guidelines
1. Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

1.1.10. Supply Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 10.  Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCP Power VCCP supplies power to the periphery.

VCC, VCCP, and VCCERAM must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator unless the SmartVID feature is used, as described below.

You can operate -1 and -2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3 speed grade device only at 0.9V typical value. Operating at 0.95 V results in higher core performance and higher power consumption. For more information about the performance and power consumption, refer to the Quartus® Prime software timing reports and Arria® 10 Early Power Estimator (EPE).

For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Arria® 10 Device Datasheet.

Use the Arria® 10 Early Power Estimator (EPE) to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. Refer to notes 2, 3, 4, 5, 6, and 10 in the Notes to Arria® 10 GX and GT Pin Connection Guidelines section.

VCC Power VCC supplies power to the core. VCC also supplies power to the Hard IP for PCI Express cores.

VCC, VCCP, and VCCERAM must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator unless the SmartVID feature is used, as described below.

You can operate -1 and -2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3 speed grade device only at 0.9V typical value. Operating at 0.95V results in higher core performance and higher power consumption. For more information about the performance and power consumption, refer to the Quartus® Prime software timing reports and Arria® 10 Early Power Estimator (EPE).

For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Arria® 10 Device Datasheet.

Use the Arria® 10 Early Power Estimator (EPE) to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. Refer to notes 2, 3, 4, 5, 6, and 10 in the Notes to Arria® 10 GX and GT Pin Connection Guidelines section.

VCCPT Power Power supply for the programmable power technology and I/O pre-drivers.

Connect VCCPT to a 1.8V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:

  • VCCH_GXB, VCCA_PLL, VCCPLL_HPS with proper isolation filtering
  • VCCIOREF_HPS
  • VCCBAT if it is using the same voltage level and the design security key feature is not required

If you are not using HPS, do not share VCCPLL_HPS and VCCIOREF_HPS with VCCPT.

Provide a minimum decoupling of 1uF for the VCCPT power rail near the VCCPT pin.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Arria® 10 Devices.

Refer to notes 2, 3, 4, 7, and 10 in the Notes to Arria® 10 GX and GT Pin Connection Guidelines section.

VCCA_PLL Power PLL analog power.

Connect VCCA_PLL to a 1.8V low noise switching regulator. With proper isolation filtering, you have the option to source VCCA_PLL from the same regulator as VCCPT.

Refer to notes 2, 3, 4, 7, and 10 in the Notes to Arria® 10 GX and GT Pin Connection Guidelines section.

VCCIO([2][A, F,G,H,I,J,K, L, AF, KL], [3][A, B,C,D,E,F,G, H, AB, GH]) Power These are I/O supply voltage pins for banks 1 through 12. Each bank can support a different voltage level. Supports VCCIO standards that include Diff HSTL/HSTL(12, 15, 18), Diff SSTL/SSTL(12, 125, 135, 15, 18), Diff HSUL/HSUL(12), Diff POD 12, LVDS/Mini_LVDS/RSDS, 1.2V, 1.5V, 1.8V, 2.5V, 3.0V I/O standards.

Connect these pins to 1.2V, 1.25V, 1.35V, 1.5V, 1.8V, 2.5V, or 3.0V supplies, depending on the I/O standard required by the specified bank. When these pins require the same voltage level as VCCPGM, you have the option to tie them to the same regulator as VCCPGM. Not all I/O banks support 2.5 V or 3.0 V supplies. Not all devices support 3.0 V I/O standard. For more details, refer to the I/O and High Speed I/O in Arria® 10 Devices in the Arria® 10 Core Fabric and General Purpose I/Os Handbook.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Arria® 10 Devices.

Refer to notes 2, 3, 4, 8, and 10 in the Notes to Arria® 10 GX and GT Pin Connection Guidelines.

VCCPGM Power Configuration pins power supply.

Connect these pins to a 1.2 V, 1.5 V, or 1.8 V power supply. When dual-purpose configuration pins are used for configuration, tie VCCIO of the bank to the same regulator as VCCPGM, ranging from 1.2 V, 1.5 V, or 1.8 V. When you do not use dual-purpose configuration pins for configuration, connect VCCIO to 1.2 V, 1.25 V, 1.35 V, 1.5 V, or 1.8 V.

When these pins require the same voltage level as VCCIO, you have the option to tie them to the same regulator as VCCIO.

Provide a minimum decoupling of 47 nF for the VCCPGM power rail near the VCCPGM pin.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Arria® 10 Devices.

Refer to notes 2, 3, 4, and 10 in the Notes to Arria® 10 GX and GT Pin Connection Guidelines section.

VCCERAM Power Memory power pins.

Connect all VCCERAM pins to a 0.9 V or 0.95 V linear or low noise switching power supply.

You have the option to share VCCL_HPS with VCCERAM plane if the VCCL_HPS voltage is at the same level for Arria® 10 SX devices.

VCC, VCCP, and VCCERAM must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. When sharing the same regulator for VCCERAM, VCC, and VCCP, the SmartVID feature is not available. If you use the SmartVID feature, then VCC and VCCP need to be sourced by a dedicated regulator that is separate from the VCCERAM regulator.

When you use the SmartVID feature, VCCERAM must be equal to 0.9 V.

Refer to notes 2, 3, 7, and 10 in the Notes to Arria® 10 GX and GT Pin Connection Guidelines section.

VCCBAT Power Battery back-up power supply for design security volatile key register.

When using the design security volatile key, connect this pin to a non-volatile battery power source in the range of 1.2 V–1.8 V.

When not using the volatile key, tie this pin to a supply ranging from more than 1.5 V to 1.8 V. If 1.8 V is selected when the design security key is unused, you have the option to source this pin from the same regulator as VCCPT.

This pin must be properly powered as per the recommended voltage range as the POR circuitry of the Arria® 10 devices monitoring VCCBAT.

Provide a minimum decoupling of 47 nF for the VCCBAT power rail near the VCCBAT pin.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Arria® 10 Devices.

GND Ground Device ground pins. All GND pins should be connected to the board ground plane.
VREFB[[2][A, F,G,H,I,J,K, L], [3][A, B,C,D,E,F,G, H]]N0 Power Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then use these pins as voltage-reference pins for the bank.

If VREF pins are not used, connect them to either the VCCIO in the bank in which the pin resides or GND. Refer to notes 2, 8, 10, and 11 in the Notes to Arria® 10 GX and GT Pin Connection Guidelines section.

The following lists the four pairs of VREF pins in the RF40 package of the Arria® 10 GX devices that must be connected to the same voltage source on the board:

  • VREFB2AN0 and VREFB2FN0
  • VREFB2KN0 and VREFB2LN0
  • VREFB3AN0 and VREFB3BN0
  • VREFB3GN0 and VREFB3HN0
VCCLSENSE Power Differential sense line to external regulator.

VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power. Connect your regulators’ differential remote sense lines to the respective VCCLSENSE and GNDSENSE pins. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source.

Connect VCCLSENSE and GNDSENSE lines to the regulator's remote sense inputs when ICC current > 30 A or when the SmartVID feature is used.

VCCLSENSE and GNDSENSE line connections are optional if ICC current <= 30 A and the SmartVID feature is not used. However, Altera recommends connecting the VCCLSENSE and GNDSENSE for regulators that support remote sense line feature.

If you do not use the VCCLSENSE and GNDSENSE pins, leave the VCCLSENSE and GNDSENSE pins unconnected.

GNDSENSE Ground
ADCGND Ground Dedicated quiet ground.

If you are using voltage sensor, you must connect ADCGND plane to board GND through a proper isolation filter with ferrite bead. Select the ferrite bead according to the frequency of the noise profile when it shows the maximum noise level. Alternatively, you can choose the ferrite bead based on the ADCGND maximum current value as well, which is 10 mA.

If you are not using voltage sensor, isolation filter with ferrite bead to board GND is optional.

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