Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
1.1.8. Reference Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
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RZQ_[#] , VID_EN | I/O | Reference pins for I/O banks. The RZQ pins share the same VCCIO with the I/O bank where they are located. Connect the external precision resistor to the designated pin within the bank. If not required, this pin is a regular I/O pin. | When using OCT tie these pins to GND through either a 240-Ω or 100-Ω resistor, depending on the desired OCT impedance. Refer to the Arria® 10 Device Handbook for the OCT impedance options for the desired OCT scheme. If you are using the Early I/O Release feature in the Arria® 10 SX devices, ensure that this pin is located within the active HPS I/O banks. For more information, refer to the HPS EMIF Design Consideration chapter of the Arria® 10 SoC Design Guidelines. |
The VID_EN pin is not a physical pin. The VID_EN pin is a multi-function shared pin with the RZQ_2A pin. | If you are using the SmartVID feature, you have the option to enable the VID_EN function using the RZQ_2A pin. If you use the RZQ_2A pin as the VID_EN pin, you cannot use the RZQ_2A pin for OCT calibration. If you are using the RZQ_2A pin for OCT calibration, you have the option to use other available general-purpose I/O pins for the VID_EN function. |
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DNU | Do Not Use | Do Not Use (DNU). | Do not connect to power, GND, or any other signal. These pins must be left floating. |
NC | No Connect | Do not drive signals into these pins. | When designing for device migration, you have the option to connect these pins to either power, GND, or a signal trace depending on the pin assignment of the devices selected for migration. However, if device migration is not a concern, leave these pins floating. |