Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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Document Table of Contents

Document Revision History for the Intel® Arria® 10 Device Datasheet

Document Version Changes
2022.02.14
  • Added TJ specifications for Military devices in the Recommended Operating Conditions for Intel® Arria® 10 Devices table.
  • Removed table description from the I/O Pin Leakage Current for Intel® Arria® 10 Devices table.
  • Changed I/O standards from RSDS (HIO) to RSDS and Mini-LVDS (HIO) to Mini-LVDS in the Differential I/O Standards Specifications for Intel® Arria® 10 Devices table.
  • Updated the conditions for VICM (AC and DC coupled) in the Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices — Receiver Specifications table.
  • Removed diagram: DPA Lock Time Specifications with DPA PLL Calibration Enabled.
  • Added footnote to Maximum Data Transition in the DPA Lock Time Specifications for Intel® Arria® 10 Devices table.
  • Updated the Configuration Bit Stream Sizes for Intel® Arria® 10 Devices table.
    • Updated table description.
    • Updated Uncompressed Configuration Bit Stream Size and IOCSR Bit Stream Size.
  • Updated Minimum Configuration Time in the Minimum Configuration Time Estimation for Intel® Arria® 10 Devices table.
2020.06.26 Removed the note on HPS_PORSEL from tRAMP in the Recommended Operating Conditions for Intel® Arria® 10 Devices table. HPS_PORSEL pin is not available for Intel® Arria® 10 devices.
2020.03.20 Corrected Th from 10 ns to 0 ns in the Management Data Input/Output (MDIO) Timing Requirements for Intel® Arria® 10 Devices table.
2019.06.24
  • Updated the definitions for the power options.
  • Updated the note to the speed grades in the High-Speed I/O Specifications for Intel® Arria® 10 Devices table.
  • Updated the definition and added a waveform for VIX in the Glossary.
2018.11.29 Removed tR and tF specifications in the FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel® Arria® 10 Devices table.
2018.09.24 Removed specifications for automotive-grade devices (–A3 speed grade).
2018.06.15
  • Added Intel® Arria® 10 Devices Overshoot Duration figure and description.
  • Removed Equation for OCT Variation Without Recalibration.
  • Updated the descriptions for Tdssfrst, Tdsslst, Tsu, and Th in the Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Intel® Arria® 10 Devices table.
  • Updated the column header from "Minimum Number of Clock Cycles" to "Number of Clock Cycles for Initialization" in the Initialization Clock Source Option and the Maximum Frequency for Intel® Arria® 10 Devices table.
2018.04.06
  • Added notes to IOUT specification in the Absolute Maximum Ratings for Intel® Arria® 10 Devices table.
  • Updated the maximum frequency for DDR3L SDRAM in the Memory Standards Supported by the HPS Hard Memory Controller for Intel® Arria® 10 Devices table.
Date Version Changes
January 2018 2018.01.09
  • Added –E1H and –I1H speed grades.
  • Removed –E2V and –I2V speed grades.
  • Added a note to the –A3 speed grade to state that the specifications for automotive-grade devices are preliminary, pending characterization.
  • Updated the Recommended Operating Conditions for Intel® Arria® 10 Devices table.
    • Added a note to VI
    • Removed the note to TJ for Industrial and Automotive devices. Note removed: –40°C is only applicable to Start of Test, when the device is powered-on. The device does not stay at the minimum junction temperature for a long time.
  • Updated the note to RSDS (HIO) and Mini-LVDS (HIO) in the Differential I/O Standards Specifications for Intel® Arria® 10 Devices table.
  • Added KDB link on PLL jitter compensation in the following tables:
    • Fractional PLL Specifications for Intel® Arria® 10 Devices
    • I/O PLL Specifications for Intel® Arria® 10 Devices
  • Corrected the clock name from "osc1 clock" to osc1_clk and added a note in the HPS Reset Input Requirements for Intel® Arria® 10 Devices table.
  • Added description about the HPS_CLK1 pin in the HPS PLL Input Requirements section.
  • Updated the note for Tsu and Th in the Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel® Arria® 10 Devices table.
  • Updated the note to CLKUSR in the Initialization Clock Source Option and the Maximum Frequency for Intel® Arria® 10 Devices table.
  • Updated the I/O Timing section on the I/O timing information generation guidelines.
  • Updated the description and maximum offset values in the IOE Programmable Delay for Intel® Arria® 10 Devices table.
June 2017 2017.06.16
  • Added specifications for automotive-grade devices.
  • Removed –E1L and –I1L speed grades.
  • Clarified the voltage requirement footnote for PCIe Gen3 support in the "Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GX/SX Devices" table.
  • Added notes for TJ for Industrial and Automotive devices in Recommended Operating Conditions for Intel® Arria® 10 Devices table.
  • Updated the description for VCCH_GXB in the following tables:
    • Absolute Maximum Ratings for Intel® Arria® 10 Devices
    • Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GX/SX Devices
    • Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GT Devices
  • Added full pin names in the "Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GX/SX Devices" table.
  • Clarified that the channel span for the x1 and x6 clock networks is six channels in a single bank in the "Transceiver Clock Network Maximum Data Rate Specifications" table.
  • Updated fVCO specifications in Fractional PLL Specifications for Intel® Arria® 10 Devices table.
  • Updated the following tables to keep only the maximum frequencies:
    • Memory Standards Supported by the Hard Memory Controller for Intel® Arria® 10 Devices
    • Memory Standards Supported by the Soft Memory Controller for Intel® Arria® 10 Devices
    • Memory Standards Supported by the HPS Hard Memory Controller for Intel® Arria® 10 Devices
  • Updated the description for Memory Output Clock Jitter Specifications for Intel® Arria® 10 Devices table.
  • Updated the unit for "Cold reset deassertion to BSEL sampling, using osc1 clock" in HPS Reset Input Requirements for Intel® Arria® 10 Devices table.
  • Updated the name of the internal reference clock to SPI_REF_CLK in the footnote in the following tables:
    • SPI Master Timing Requirements for Intel® Arria® 10 Devices
    • SPI Slave Timing Requirements for Intel® Arria® 10 Devices
  • Updated maximum values for tCF2CD from 600 ns to 1,440 ns and tCF2ST0 from 600 ns to 960 ns in the following tables:
    • FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel® Arria® 10 Devices
    • FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel® Arria® 10 Devices
    • PS Timing Parameters for Intel® Arria® 10 Devices
May 2017 2017.05.08
  • Updated VCCBAT specifications in Recommended Operating Conditions for Intel® Arria® 10 Devices table.
  • Changed the maximum skew specification for the xN clock line in the "Transmitter Channel-to-channel Skew Specifications" table.
  • Changed the PCIe Gen3 HIP-Fabric interface spec for E3S and I3S devices in the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices" table.
  • Changed the conditions for VICM in the "Receiver Specifications" table.
  • Removed the DC Coupling specifications footnote from the "Receiver Specifications" table.
  • Changed the conditions for the differential on-chip termination resistors parameter in the "Transmitter Specifications" table.
  • Updated the footnote for VICM (AC and DC coupled) parameter in the "Receiver Specifications" table.
  • Added footnotes to the minimum specifications for the fPLL input reference clock frequency in the "Reference Clock Specifications" table depending on the selected mode.
  • Changed the Core Speed Grade options in the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices" table.
  • Added information on power supply using early I/O release configuration flow in HPS Specifications section.
  • Added description in the Configuration Bit Stream Sizes for Intel® Arria® 10 Devices table.
March 2017 2017.03.15
  • Changed the minimum value for the fPLL input reference clock frequency in the "Reference Clock Specifications" table.
  • Added a footnote to the Supported I/O Standards parameter in the "Receiver Specifications" table.
  • Added a footnote to VCCR_GXB[L, R] and VCCT_GXB[L, R] in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices" table.
  • Added fCASC_INPFD specification in the following tables:
    • Fractional PLL Specifications for Intel® Arria® 10 Devices
    • I/O PLL Specifications for Intel® Arria® 10 Devices
  • Updated links to the External Memory Interface Spec Estimator in the following sections:
    • Memory Standards Supported by the Hard Memory Controller
    • Memory Standards Supported by the Soft Memory Controller
    • Memory Standards Supported by the HPS Hard Memory Controller
  • Updated Maximum HPS Clock Frequencies Across Device Speed Grades for Intel® Arria® 10 Devices table.
    • Removed temperature ranges.
    • Updated mpu_base_clk specification from 1,000 MHz to 1,200 MHz in –1 speed grade for VCCL_HPS = 0.9 V (typical).
  • Updated HPS PLL VCO output maximum specification from 2,000 MHz to 2,400 MHz in -1 speed grade for VCCL_HPS = 0.9 V in HPS PLL Performance for Intel® Arria® 10 Devices table.
  • Updated links to the Intel® Arria® 10 SoC Device Design Guidelines in the following sections:
    • USB ULPI Timing Characteristics
    • Ethernet Media Access Controller (EMAC) Timing Characteristics
  • Updated uncompressed configuration bit stream size (bits) in Configuration Bit Stream Sizes for Intel® Arria® 10 Devices table.
  • Added descriptions for Programmable IOE Delay.
  • Removed PowerPlay text from tool name.
  • Rebranded as Intel.
October 2016 2016.10.31
  • Added reference to the Intel® Arria® 10 SoC Device Design Guidelines for the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel® Arria® 10 Devices table.
  • Added reference to the Intel® Arria® 10 SoC Device Design Guidelines for the RGMII RX Timing Requirements for Intel® Arria® 10 Devices table.
  • Updated the fVCO values in the Fractional PLL Specifications for Intel® Arria® 10 Devices table.
  • Updated the tOUTPJ_DC and tOUTCCJ_DC values in the I/O PLL Specifications for Intel® Arria® 10 Devices table.
  • Updated the description to the DPA Lock Time Specifications for Intel® Arria® 10 Devices table as the specifications are applicable to both extended and industrial grades.
  • Updated the description to the Maximum HPS Clock Frequencies Across Device Speed Grades for Intel® Arria® 10 Devices table as the specifications are applicable to both extended and industrial temperatures.
  • Removed Preliminary tag for the Trace Timing Requirements for Intel® Arria® 10 Devices table.
  • Changed the condition for the slew rate setting in the "Transmitter Specifications" table.
June 2016 2016.06.24
  • Updated VCCL_HPS specifications in HPS Power Supply Operating Conditions for Intel® Arria® 10 SX Devices table.
  • Restructured the following tables:
    • OCT Calibration Accuracy Specifications for Intel® Arria® 10 Devices
    • OCT Without Calibration Resistance Tolerance Specifications for Intel® Arria® 10 Devices
  • Removed PCML information in Differential I/O Standards Specifications for Intel® Arria® 10 Devices table.
  • Changed values in the "Transmitter and Receiver Data Rate Performance" table.
  • Updated specifications for memory standards supported by the hard memory controller, soft memory controller, and HPS hard memory controller.
  • Updated DLL operating frequency range in DLL Frequency Range Specifications for Intel® Arria® 10 Devices table.
  • Updated Memory Output Clock Jitter Specifications for Intel® Arria® 10 Devices table.
  • Updated HPS Clock Performance specifications.
  • Updated HPS PLL Performance for Intel® Arria® 10 Devices table.
    • Updated HPS PLL VCO output –3 speed grade maximum specification for 0.95 V VCCL_HPS.
    • Added HPS PLL VCO output specifications for 0.90 V VCCL_HPS.
    • Added h2f_user0_clk and h2f_user1_clk specifications.
  • Added a new table for HPS PLL Output Specifications.
  • Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Intel® Arria® 10 Devices table.
    • Updated QSPI_CLK clock name.
    • Updated Tclk, Tdssfrst, Tdsslst, and Tdo specifications.
    • Added Tsu and Th specifications.
    • Removed Tdin_start and Tdin_end specifications.
  • Updated Tdssfrst, Tdsslst, Tdio, and Tsu specifications in SPI Master Timing Requirements for Intel® Arria® 10 Devices table.
  • Updated Th and Td specifications in SPI Slave Timing Requirements for Intel® Arria® 10 Devices table.
  • Updated Tsu, Th, and Td specifications in Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel® Arria® 10 Devices table.
  • Added a note to Td in Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel® Arria® 10 Devices table.
  • Updated Th specifications in RGMII RX Timing Requirements for Intel® Arria® 10 Devices table.
  • Updated Td specifications in RMII TX Timing Requirements for Intel® Arria® 10 Devices table.
  • Added notes in I2C Timing Requirements for Intel® Arria® 10 Devices table.
  • Updated Trace Timing Requirements for Intel® Arria® 10 Devices table.
    • Added description about increasing trace bandwidth.
    • Updated Tclk minimum specification from 5 ns to 10 ns.
  • Updated the information on GPIO interface.
  • Updated the following timing diagrams:
    • Quad SPI Flash Serial Output Timing Diagram
    • Quad SPI Flash Serial Input Timing Diagram
    • SPI Master Output Timing Diagram
    • SPI Master Input Timing Diagram
    • SPI Slave Output Timing Diagram
    • SPI Slave Input Timing Diagram
    • I2C Timing Diagram
    • NAND Address Latch Timing Diagram
    • NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
    • NAND Read Status Timing Diagram
    • Trace Timing Diagram
  • Updated DCLK Frequency Specification in the AS Configuration Scheme table.
  • Updated IOCSR bit stream sizes in Configuration Bit Stream Sizes for Intel® Arria® 10 Devices table.
  • Corrected product line naming in the following tables:
    • Configuration Bit Stream Sizes for Intel® Arria® 10 Devices
    • Minimum Configuration Time Estimation for Intel® Arria® 10 Devices
  • Updated IOE Programmable Delay for Intel® Arria® 10 Devices table.
  • Removed Preliminary tags for all tables, except Trace Timing Requirements for Intel® Arria® 10 Devices table.
May 2016 2016.05.02
  • Updated Recommended Operating Conditions for Intel® Arria® 10 Devices table.
    • Added specifications for 0.95 V typical value for VCC, VCCP, and VCCERAM.
    • Updated SmartVID specifications for VCC and VCCP.
    • Updated notes to VCC, VCCP, VCCERAM, and VCCBAT.
  • Updated specifications for SSTL-12 240-Ω RS, SSTL-135 34-Ω RS, and SSTL-135 40-Ω RS in OCT Calibration Accuracy Specifications for Intel® Arria® 10 Devices table.
  • Removed the condition VCCIO = 1.5 for 100-Ω RD in OCT Without Calibration Resistance Tolerance Specifications for Intel® Arria® 10 Devices table.
  • Changed pin capacitance to maximum values.
  • Added SSTL-135 Class I, II, SSTL-125 Class I, II, and SSTL-12 Class I, II I/O standards in the following tables:
    • Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel® Arria® 10 Devices
    • Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel® Arria® 10 Devices
    • Differential SSTL I/O Standards Specifications for Intel® Arria® 10 Devices
  • Corrected VOD specifications for Mini-LVDS (HIO) to 0.6 V in Differential I/O Standards Specifications for Intel® Arria® 10 Devices table.
  • Changed the backplane data rates in the "Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GX/SX Devices" table.
  • Changed the conditions and backplane data rates in the "Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GT Devices" table.
  • Changed the backplane data rates in the "Transceiver Performance for Intel® Arria® 10 GX/SX Devices" section.
  • Changed the backplane data rates in the "Transceiver Performance for Intel® Arria® 10 GT Devices" section.
  • Changed the minimum frequency in the "CMU PLL Performance" table.
  • Changed the conditions and added a description to the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices" table.
  • Removed transceiver speed grade 5 from all tables in the "Transceiver Performance for Intel® Arria® 10 GX/SX Devices" section.
  • Changed the notes in the "Transmitter and Receiver Data Rate Performance" table.
  • Added a description to the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices" table.
  • Changed the clock network names in the "Transceiver Clock Network Maximum Data Rate Specifications" table.
  • Changed the conditions in the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices" table.
  • Changed the channel span specifications in the "Transmitter Channel-to-channel Skew Specifications" table.
  • Updated fVCO, fCLBW, tPLL_PSERR, and jitter specifications in Fractional PLL Specifications for Intel® Arria® 10 Devices table.
  • Updated tOUTDUTY and jitter specifications in I/O PLL Specifications for Intel® Arria® 10 Devices table.
  • Updated the note to fIN specifications for fPLL and IOPLL.
  • Updated High-Speed I/O Specifications for Intel® Arria® 10 Devices table.
    • Added true RSDS and true mini-LVDS output standards data rates.
    • Updated speed grades to reflect SmartVID specifications.
    • Updated Transmitter fHSDR and Receiver fHSDRDPA specifications.
    • Added minimum data rate for Receiver fHSDRDPA specifications.
  • Updated LVDS I/O bank and 3 V I/O bank specifications, and added SmartVID specifications in Memory Standards Supported by the Hard Memory Controller for Intel® Arria® 10 Devices and Memory Standards Supported by the Soft Memory Controller for Intel® Arria® 10 Devices tables.
  • Added new table: Memory Standards Supported by the HPS Hard Memory Controller for Intel® Arria® 10 Devices.
  • Updated tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and AS ×4 Configurations in Intel® Arria® 10 Devices table.
  • Added IOCSR definition and updated column heading from "IOCSR .rbf Size (bits)" to "IOCSR Bit Stream Size (bits)" in Configuration Bit Stream Sizes for Intel® Arria® 10 Devices table.
  • Removed M suffix and VCC PowerManager feature.
February 2016 2016.02.11
  • Changed the datarates in the "Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GT Devices" table.
  • Changed the available speed grades and datarates in the "Transceiver Performance for Intel® Arria® 10 GT Devices" table.
  • Changed the available speed grades and datarates in the "ATX PLL Performance" table.
  • Changed the available speed grades and datarates in the "Fractional PLL Performance" table.
  • Changed the available speed grades in the "CMU PLL Performance" table.
  • Changed the available speed grades and frequencies in the "High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GT Devices" table.
December 2015 2015.12.31
  • Updated M20K block specifications for "True dual port, all supported widths" and "ROM, all supported widths" in the Memory Clock Performance Specifications (VCC and VCCP at 0.9 V Typical Value) table.
  • Updated maximum resolution from 8 bit 6 bit and added minimum clock frequency of 0.1 MHz in Internal Voltage Sensor Specifications for Intel® Arria® 10 Devices table.
  • Updated the sinusoidal jitter from 0.35 UI to 0.28 UI in LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications.
December 2015 2015.12.18
  • Changed the minimum specifications in the "Transceiver Power Supply Operating Conditions for Arria 10 GT Devices" table.
  • Changed conditions in the "Transmitter and Receiver Data Rate Performance" table.
November 2015 2015.11.02
  • Added power option V which is supported with the SmartVID feature (lowest static power).
  • Added note for SmartVID in Recommended Operating Conditions for Intel® Arria® 10 Devices table. Note: SmartVID is supported in devices with –2V and –3V speed grades only.
  • Removed 20-Ω RT in OCT Calibration Accuracy Specifications for Intel® Arria® 10 Devices table.
  • Updated specifications in OCT Without Calibration Resistance Tolerance Specifications for Intel® Arria® 10 Devices table.
  • Updated the note for Value column in the Internal Weak Pull-Up Resistor Values for Intel® Arria® 10 Devices table. Added Internal Weak Pull-Down Resistor Values for Intel® Arria® 10 Devices table.
  • Updated fractional PLL specifications:
    • Updated fIN minimum from 50 MHz to 30 MHz and maximum from 1000 MHz to 800 MHz for all speed grades.
    • Updated fINPFD minimum from 50 MHz to 30 MHz and maximum from 325 MHz to 700 MHz.
    • Updated fVCO minimum from 3.125 GHz to 3.5 GHz and maximum from 6.25 GHz to 7.05 GHz.
    • Updated tEINDUTY minimum from 40% to 45% and maximum from 60% to 55%.
    • Removed the conditions for fOUT and fCLBW.
    • Updated the descriptions for fDYCONFIGCLK, tLOCK, and tARESET.
  • Added –E2V, –I2V, –E3V, and –I3V speed grades in DSP Block Performance Specifications for Intel® Arria® 10 Devices (VCC and VCCP at 0.9 V Typical Value) table.
  • Updated Memory Block Performance Specifications for Intel® Arria® 10 Devices table for VCC and VCCP at 0.9 V typical value. Added memory block performance specifications for VCC and VCCP at 0.95 V typical value.
  • Removed the "Minimum Resolution with no Missing Codes" column in Internal Temperature Sensing Diode Specifications for Intel® Arria® 10 Devices table.
  • Added a link in the Internal Temperature Sensing Diode Specifications section: Transfer Function for Internal TSD topic in the Power Management in Intel® Arria® 10 Devices chapter, Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook.
  • Added descriptions to External Temperature Sensing Diode Specifications for Intel® Arria® 10 Devices table.
  • Updated Internal Voltage Sensor Specifications for Intel® Arria® 10 Devices table.
    • Updated maximum resolution from 12 bits to 8 bits. Removed minimum resolution value.
    • Updated maximum integral non-linearity (INL) from ±3 LSB to ±1 LSB.
    • Updated maximum clock frequency from 20 MHz to 11 MHz.
    • Added gain error and offset error specifications.
    • Removed signal to noise and distortion ratio (SNR) specifications.
    • Removed Bipolar input mode specifications.
  • Updated "slow clock" to "core clock" in DPA Lock Time Specifications with DPA PLL Calibration Enabled diagram.
  • Updated the maximum values of the following conditions for Transmitter True Differential I/O Standards - fHSDR (data rate) parameter in High-Speed I/O Specifications for Intel® Arria® 10 Devices table.
    • SERDES factor J = 2, uses DDR registers
    • SERDES factor J = 1, uses DDR registers
  • Added the following tables:
    • Memory Standards Supported by the Hard Memory Controller for Intel® Arria® 10 Devices
    • Memory Standards Supported by the Soft Memory Controller for Intel® Arria® 10 Devices
  • Updated minimum TOCTCAL value from 1000 cycles to 2000 cycles in OCT Calibration Block Specifications for Intel® Arria® 10 Devices table.
  • Updated the hmc_free_clk specifications for the following speed grades in HPS Clock Performance for Intel® Arria® 10 Devices table:
    • –1 speed grade: Updated from 667 MHz to 533 MHz.
    • –2 speed grade: Updated from 544 MHz to 533 MHz.
  • Changed from Tsclk to Tclk and added the following specifications in the Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Intel® Arria® 10 Devices table.
    • Tqspi_clk
    • Tdin_start
    • Tdin_end
  • Updated SPI Master Timing Requirements for Intel® Arria® 10 Devices table.
    • Changed the symbol from Tspi_clk to Tclk.
    • Added note to Tdssfrst, Tdsslst, and Th.
    • Updated note to Tsu.
    • Updated the description for Tsu and Th.
  • Updated the note to Tssfsu, Tssfh, Tsslsu, and Tsslh in the SPI Slave Timing Requirements for Intel® Arria® 10 Devices table.
  • Updated the following timing diagrams:
    • Quad SPI Flash Serial Output Timing Diagram
    • SPI Master Output Timing Diagram
    • SPI Slave Output Timing Diagram
  • Added the following timing diagrams:
    • Quad SPI Flash Serial Input Timing Diagram
    • SPI Master Input Timing Diagram
    • SPI Slave Input Timing Diagram
  • Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel® Arria® 10 Devices table.
    • Changed Tclk to Tsdmmc_clk_out and TMMC_CLK to TSDMMC_CLK_OUT.
    • Updated Td min from 5.5 ns to 8.5 ns and max from 12.5 ns to 11.5 ns.
    • Updated note to Td.
  • Changed the title and symbols in the following timing diagrams:
    • Changed from "NAND Data Input Cycle Timing Diagram" to "NAND Data Output Cycle Timing Diagram". Changed from DIN to DOUT.
    • Changed from "NAND Data Output Cycle Timing Diagram" to "NAND Data Input Cycle Timing Diagram". Changed from DOUT to DIN.
    • Changed from "NAND Extended Data Output (EDO) Cycle Timing Diagram" to "NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle". Changed from DOUT to DIN.
  • Changed from "ARM Trace Timing Characteristics" to "Trace Timing Characteristics".
  • Updated the description in the GPIO Interface topic.
  • Updated FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel® Arria® 10 Devices table.
    • Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 μs to 3,000 μs.
    • Updated fMAX for FPP ×8/×16 from 125 MHz to 100 MHz.
    • Updated the minimum value for tCF2CK from 1,506 μs to 3,010 μs.
    • Updated the minimum value for tST2CK from 2 μs to 10 μs.
    • Updated the maximum value for tCD2UM from 437 μs to 830 μs.
  • Updated FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel® Arria® 10 Devices table.
    • Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 μs to 3,000 μs.
    • Updated fMAX for FPP ×8/×16 from 125 MHz to 100 MHz.
    • Updated the minimum value for tCF2CK from 1,506 μs to 3,010 μs.
    • Updated the minimum value for tST2CK from 2 μs to 10 μs.
    • Updated the maximum value for tCD2UM from 437 μs to 830 μs.
  • Updated maximum value for tCD2UM from 437 μs to 830 μs in AS Timing Parameters for AS ×1 and AS ×4 Configurations in Intel® Arria® 10 Devices table.
  • Updated PS Timing Parameters for Intel® Arria® 10 Devices table.
    • Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 μs to 3,000 μs
    • Updated the minimum value for tCF2CK from 1,506 μs to 3,010 μs.
    • Updated the minimum value for tST2CK from 2 μs to 10 μs.
    • Updated the maximum value for tCD2UM from 437 μs to 830 μs.
  • Added description about .rbf and .rpd files in the Configuration Files section. Changed the table title from "Uncompressed Uncompressed .rbf Sizes Sizes for Intel® Arria® 10 Devices" to "Configuration Bit Stream Sizes for Intel® Arria® 10 Devices".
  • Updated the note to Active Serial in Minimum Configuration Time Estimation for Intel® Arria® 10 Devices table. Note: The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSR may guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table.
  • Changed instances of Quartus II to Quartus Prime.
  • Changed voltages and conditions in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices" table.
  • Changed maximum data rate conditions in the "Transmitter and Receiver Data Rate Performance" table.
  • Changed conditions in the "Transmitter and Receiver Data Rate Performance" table in the Transceiver Performance for Arria 10 GT Devices section.
  • Changed conditions in the "Reference Clock Specifications" table.
  • Changed the clock networks in the "Transceiver Clock Network Maximum Data Rate Specifications" table.
  • Changed conditions in the "Receiver Specifications" table.
  • Changed conditions in the "Transmitter Specifications" table.
  • Changed the minimum frequency in the "ATX PLL Performance," "Fractional PLL Performance," and "CMU PLL Performance" tables in the Transceiver Performance for Intel® Arria® 10 GX/SX Devices section.
  • Changed the minimum frequeny in the "ATX PLL Performance," "Fractional PLL Performance," and "CMU PLL Performance" tables in the Transceiver Performance for Intel® Arria® 10 GT Devices section.
  • Added a parameter to the "Reference Clock Specifications" table.
  • Added footnote to the "Transmitter Specifications" table.
June 2015 2015.06.12
  • Changed the specifications for the backplane maximum data rate condition in the "Transmitter and Receiver Data Rate Performance" table for Intel® Arria® 10 GX/SX devices.
  • Changed the specifications for transmitter REFCLK phase noise in the "Reference Clock Specifications" table.
  • Added note in the following tables:
    • Absolute Maximum Ratings for Intel® Arria® 10 Devices: VCCPGM
    • Maximum Allowed Overshoot During Transitions for Intel® Arria® 10 Devices: LVDS I/O
    • Recommended Operating Conditions for Intel® Arria® 10 Devices: VI
  • Added HPS Specifications.
  • Updated recommended EPCQ-L serial configuration devices in the Uncompressed .rbf Sizes table.
May 2015 2015.05.08 Made the following changes:
  • Changed the specifications for the VICM (AC coupled) parameter in the "Reference Clock Specifications" table.
  • Changed the maximum frequency in the "CMU PLL Performance" table in the Transceiver Performance for GT Devices section.
  • Added a footnote to the transceiver speed grade 5 column in the "Transmitter and Receiver Data Rate Performance" table.
May 2015 2015.05.04
  • Updated the Maximum Allowed Overshoot During Transitions for Intel® Arria® 10 Devices table.
  • Added a note to tramp in the Recommended Operating Conditions for Intel® Arria® 10 Devices table. Note: tramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
  • Changed the minimum, typical, and maximum values for the transmitter and receiver power supply in the "Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GT Devices" table.
  • Added –1 speed grade in the condition column for VCCL_HPS at 0.95 V in HPS Power Supply Operating Conditions for Intel® Arria® 10 SX Devices table.
  • Added –I1S, –I2S, and –E2S speed grades to the following tables:
    • Clock Tree Performance for Intel® Arria® 10 Devices
    • DSP Block Performance Specifications for Intel® Arria® 10 Devices
    • Memory Block Performance Specifications for Intel® Arria® 10 Devices
    • High-Speed I/O Specifications for Intel® Arria® 10 Devices
    • Memory Output Clock Jitter Specifications for Intel® Arria® 10 Devices
  • Updated fIN minimum value from 27 MHz to 50 MHz for all speed grades in the Fractional PLL Specifications for Intel® Arria® 10 Devices table.
  • Changed the description for fINPFD to "Input clock frequency to the PFD" in the I/O PLL Specifications for Intel® Arria® 10 Devices table.
  • Updated DSP Block Performance Specifications for Intel® Arria® 10 Devices table for VCC and VCCP at 0.9 V typical value. Added DSP specifications for VCC and VCCP at 0.95 V typical value.
  • Updated Ibias minimum value from 8 μA to 10 μA and maximum value from 200 μA to 100 μA in the External Temperature Sensing Diode Specifications for Intel® Arria® 10 Devices table.
  • Added DPA (soft CDR mode) specifications in High-Speed I/O Specifications for Intel® Arria® 10 Devices table.
  • Added description in POR Specifications section: Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration.
  • Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices chapter.
    • FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
    • FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
    • AS Configuration Timing Waveform
    • PS Configuration Timing Waveform
  • Removed the DCLK-to-DATA[] ratio when both encryption and compression are turned on. Added description to the table: You cannot turn on encryption and compression at the same time for Intel® Arria® 10 devices.
  • Updated the AS Timing Parameters for AS ×1 and AS ×4 Configurations in Intel® Arria® 10 Devices table as follows:
    • Changed the symbol for data hold time from tH to tDH.
    • Updated the minimum value for tSU from 0 ns to 1 ns.
    • Updated the minimum value for tDH from 2.5 ns to 1.5 ns.
  • Added a note to the DCLK Frequency Specification in the AS Configuration Scheme table. Note: You can only set 12.5, 25, 50, and 100 MHz in the Intel® Quartus® Prime software.
  • Added a note to the Initialization Clock Source Option and the Maximum Frequency for Intel® Arria® 10 Devices. Note: If you use the CLKUSR pin for AS and transceiver calibration simultaneously, the only allowed frequency is 100 MHz.
  • Changed Intel® Arria® 10 GS to Intel® Arria® 10 SX in Uncompressed .rbf Sizes and Minimum Configuration Time Estimation tables.
  • Added IO_IN_DLY_CHN and IO_OUT_DLY_CHN in the IOE Programmable Delay table.
  • Changed the Min/Typ/Max description for the VICM (AC coupled) parameter in the "Reference Clock Specifications" table.
  • Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices" table.
  • Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GT Devices" table.
  • Added a footnote to the maximum data rate for GT channels in the "Transceiver Performance for GT Devices" section.
  • Made the following changes to the "Transceiver Performance for Arria 10 GX/SX Devices" section.
    • Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and Receiver Data Rate Performance" table.
    • Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table.
    • Changed the minimum frequency in the "ATX PLL Performance" table.
    • Changed the minimum frequency in the "Fractional PLL Performance" table.
    • Changed the minimum and maximum frequency in the "CMU PLL Performance" table.
  • Made the following changes to the "Transceiver Performance for Arria 10 GT Devices" section.
    • Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table.
    • Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and Receiver Data Rate Performance" table.
    • Changed the minimum frequency in the "ATX PLL Performance" table.
    • Changed the minimum frequency in the "Fractional PLL Performance" table.
    • Changed the minimum frequency in the "CMU PLL Performance" table.
  • Added voltage condition to the maximum peak-to-peak diff p-p after configuration and to the VICM specifications in the "Receiver Specifications" table.
  • Changed the voltage conditions for VOCM in the "Transmitter Specifications" table.
  • Changed the VOD/VCCT Ratios in the "Typical Transmitter VOD Settings" table.
  • Added the "Transceiver Clock Network Maximum Data Rate Specifications" table.
January 2015 2015.01.23
  • Added a note in the "Transceiver Power Supply Operating Conditions" section.
  • Made the following changes to the "Reference Clock Specifications" table:
    • Added the input reference clock frequency parameters for the CMU PLL, ATX PLL, and fPLL PLL.
    • Changed the maximum specification for rise time and fall time.
    • Added the VICM (AC and DC coupled) parameters.
    • Changed the maximum value for Transmitter REFCLK Phase Noise (622 MHz) when ≥ 1 MHz.
  • Changed the Min, Typ, and Max values for the reconfig_clk signal in the "Transceiver Clocks Specifications" table.
  • Made the following changes to the "Receiver Specifications" table:
    • Added the maximum peak-to-peak differential input voltage after device configuration specifications.
    • Changed the minimum specification for the minimum differential eye opening at receiver serial input pins parameter.
    • Removed the 120-ohm and 150-ohm conditions for the differential on-chip termination resistors parameter.
    • Added the VICM (AC and DC coupled) parameter.
    • Added the Programmable DC Gain parameter.
  • Made the following changes to the "Transmitter Specifications" table:
    • Added the VOCM (AC coupled) parameter.
    • Added the VOCM (DC coupled) parameter.
    • Changed the rise and fall time minimum and maximum specifications.
  • Added the "Typical Transmitter VOD Settings" table.
  • Added a note to VCC, VCCP, and VCCERAM typical values in Recommended Operating Conditions table. Note: You can operate –1 and –2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3 speed grade device at only 0.9 V typical value. Core performance shown in this datasheet is applicable for the operation at 0.9 V. Operating at 0.95 V results in higher core performance and higher power consumption. For more information about the performance and power consumption of 0.95 V operation, refer to the Intel® Quartus® Prime software timing reports and Early Power Estimator (EPE).
  • Removed military grade operating junction temperature specifications (TJ) in Recommended Operating Conditions table.
  • Updated the VCCIO range for HSTL-18 I/O standard in Differential HSTL and HSUL I/O Standards for Arria 10 Devices table as follows:
    • Min: Updated from 1.425 V to 1.71 V
    • Typ: Updated from 1.5 V to 1.8 V
    • Max: Updated from 1.575 V to 1.89 V
  • Added a statement to Differential I/O Standards Specifications for Intel® Arria® 10 Devices table: Differential inputs are powered by VCCPT which requires 1.8 V.
  • Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
  • Updated fractional PLL specifications.
    • Updated fOUT_C to fOUT and updated the maximum value to 644 MHz for all speed grades.
    • Updated fVCO minimum value from 2.4 GHz to 3.125 GHz.
    • Removed fOUT_L, kVALUE, and fRES parameters.
  • Updated I/O PLL specifications.
    • Updated fOUT_C to fOUT and updated the maximum value to 644 MHz for all speed grades.
    • Updated fOUT_EXT maximum value to 800 MHz (–1 speed grade), 720 MHz (–2 speed grade), and 650 MHz (–3 speed grade).
    • Removed fRES parameter.
  • Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design.
  • Updated AS Timing Parameters for AS x1 and AS x4 Configurations in Intel® Arria® 10 Devices.
    • Updated tSU minimum value from 1.5 ns to 0 ns.
    • Updated tH minimum value from 0 ns to 2.5 ns.
  • Updated CLKUSR initialization clock source maximum frequency from 125 MHz to 100 MHz for passive configuration schemes (PS and FPP).
  • Added uncompressed .rbf sizes and minimum configuration time estimation for Intel® Arria® 10 GX and GS devices.
  • Updated uncompressed .rbf sizes for Intel® Arria® 10 GX 900 and 1150 devices, and Intel® Arria® 10 GT 900 and 1150 devices.
    • Updated configuration .rbf size from 335,106,890 bits to 351,292,512 bits.
    • Updated IOCSR .rbf size from 6,702,138 bits to 1,885,396 bits.
  • Updated minimum configuration time estimation for Intel® Arria® 10 GX 900 and 1150 devices, and Intel® Arria® 10 GT 900 and 1150 devices for the following configuration modes:
    • Active serial: Updated from 837.77 ms to 883.20 ms.
    • Fast Passive Parallel: Updated from 104.72 ms to 110.40 ms.
August 2014 2014.08.18
  • Changed the 3 V I/O conditions in Table 2.
  • Table 3:
    • Added a note to the Minimum and Maximum operating conditions.
    • Changed VCCERAM values.
    • Changed the Maximum recommended operating conditions for 3 V I/O VI.
  • Added a note to the I/O pin pull-up tolerance in Table 12.
  • Changed the VIH values for LVTTL, LVCMOS and 2.5 I/O standards in Table 13.
  • Table 14, Table 15, and Table 16:
    • Added SSTL-12 I/O standard.
    • Removed Class I, II for SSTL-135 and SSTL-125 I/O standards.
  • Table 19:
    • Changed the minimum data rate specification for transmitter and receiver data rates.
    • Changed the minimum frequency specification for the fractional PLL.
    • Changed the minimum frequency specification for the CMU PLL.
  • Changed the Core Speed Grade with Power Options section in Table 20.
  • Table 21:
    • Changed the minimum data rate specification for transmitter and receiver data rates.
    • Changed the minimum frequency specification for the Fractional PLL.
    • Changed the minimum frequency specification for the CMU PLL.
    • Changed the minimum frequency of the ATX PLL.
  • Table 23:
    • Added a note to the High Speed Differential I/O standard.
    • Changed the specifications for CLKUSR pin.
  • Added columns in Table 29.
  • Changed the maximum fHSCLK_in and txJitter in Table 32.
  • Changed the minimum formula for tCD2UMC in Table 42, Table 43, Table 44, and Table 46.
  • Changed the CLKUSR maximum frequency and minimum number of cycles in Table 47.
  • Table 48:
    • Changed the IOCSR .rbf size.
    • Added Recommended EPCQ-L Serial Configuration Device.
  • Changed the DCLK frequency and minimum configuration time for FPP in Table 49.
  • Added the following tables:
    • External Temperature Sensing Diode Specifications for Intel® Arria® 10 Devices
    • IOE Programmable Delay for Intel® Arria® 10 Devices
  • Removed the following figures:
    • CTLE Response in High Gain Mode for Intel® Arria® 10 Devices with Data Rates ≥ 8 Gbps
    • Removed the CTLE Response in High Gain Mode for Intel® Arria® 10 Devices with Data Rates < 8 Gbps
March 2014 2014.03.14 Updated Table 3, Table 5, Table 21, Table 23, Table 24, Table 32, and Table 41.
December 2013 2013.12.06 Updated Figure 1 and Figure 2.
December 2013 2013.12.02 Initial release.

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