Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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Internal Weak Pull-Up and Weak Pull-Down Resistor

All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. The weak pull-down feature is only available for the pins as described in the Internal Weak Pull-Down Resistor Values for Intel® Arria® 10 Devices table.

Table 12.  Internal Weak Pull-Up Resistor Values for Intel® Arria® 10 Devices
Symbol Description Condition (V) 28 Value  29 Unit
RPU Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. VCCIO = 3.0 ±5% 25
VCCIO = 2.5 ±5% 25
VCCIO = 1.8 ±5% 25
VCCIO = 1.5 ±5% 25
VCCIO = 1.35 ±5% 25
VCCIO = 1.25 ±5% 25
VCCIO = 1.2 ±5% 25
Table 13.  Internal Weak Pull-Down Resistor Values for Intel® Arria® 10 Devices
Pin Name Description Condition (V) Value 29 Unit
nIO_PULLUP Dedicated input pin that determines the internal pull-ups on user I/O pins and dual-purpose I/O pins. VCC = 0.9 ±3.33% 25 kΩ
TCK Dedicated JTAG test clock input pin. VCCPGM = 1.8 ±5 % 25 kΩ
VCCPGM = 1.5 ±5% 25 kΩ
VCCPGM = 1.2 ±5% 25 kΩ
MSEL[0:2] Configuration input pins that set the configuration scheme for the FPGA device. VCCPGM = 1.8 ±5% 25 kΩ
VCCPGM = 1.5 ±5% 25 kΩ
VCCPGM = 1.2 ±5% 25 kΩ
28 Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
29 Valid with ±25% tolerances to cover changes over PVT.

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