Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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Fractional PLL Specifications

Table 38.  Fractional PLL Specifications for Intel® Arria® 10 Devices
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency 30 800 64 MHz
fINPFD Input clock frequency to the phase frequency detector (PFD) 30 700 MHz
fCASC_INPFD Input clock frequency to the PFD of destination cascade PLL 30 60 MHz
fVCO PLL voltage-controlled oscillator (VCO) operating range 6 14.025 GHz
tEINDUTY Input clock duty cycle 45 55 %
fOUT Output frequency for internal global or regional clock 644 MHz
fDYCONFIGCLK Dynamic configuration clock for reconfig_clk 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of pll_powerdown 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 1 ms
fCLBW PLL closed-loop bandwidth 0.3 4 MHz
tPLL_PSERR Accuracy of PLL phase shift Non-SmartVID 50 ps
SmartVID 75 ps
tARESET Minimum pulse width on the pll_powerdown signal 10 ns
tINCCJ 65 66 Input clock cycle-to-cycle jitter FREF ≥ 100 MHz 0.13 UI (p-p)
FREF < 100 MHz 650 ps (p-p)
tOUTPJ 67 Period jitter for clock output FOUT ≥ 100 MHz 600 ps (p-p)
FOUT < 100 MHz 60 mUI (p-p)
tOUTCCJ 67 Cycle-to-cycle jitter for clock output FOUT ≥ 100 MHz 600 ps (p-p)
FOUT < 100 MHz 60 mUI (p-p)
dKBIT Bit number of Delta Sigma Modulator (DSM) 32 bit
64 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
65 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
66 FREF is fIN/N, specification applies when N = 1.
67 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel® Arria® 10 Devices table.

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