Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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Quad SPI Flash Timing Characteristics

Table 62.  Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Intel® Arria® 10 DevicesNote that the Intel® Arria® 10 HPS boot loader calibrates the input timing automatically.
Symbol Description Min Typ Max Unit
Tqspi_ref_clk QSPI_REF_CLK clock period 2.5 ns
Tclk QSPI_CLK clock period 9.25 ns
Tdutycycle QSPI_CLK duty cycle 45 50 55 %
Tdssfrst 89 QSPI_SS asserted to first QSPI_CLK edge 3.6 5.25 ns
Tdsslst 89 Last QSPI_CLK edge to QSPI_SS deasserted –1 1 ns
Tdo QSPI_DATA output delay 0 2.6 ns
Tsu Input setup with respect to QSPI_CLK capture edge 6.5 – (Rdelay × Tqspi_ref_clk) 90 ns
Th Input hold with respect to QSPI_CLK capture edge (Rdelay + 1) × Tqspi_ref_clk 90 ns
Tdssb2b 89 Minimum delay of slave select deassertion between two back-to-back transfer 1 QSPI_CLK
Figure 5. Quad SPI Flash Serial Output Timing Diagram
Figure 6. Quad SPI Flash Serial Input Timing Diagram
89 This delay is programmable in whole QSPI_REF_CLK increments using the delay register in the Quad SPI module.
90 Rdelay is programmable in whole QSPI_REF_CLK increments using the delay field in the rddatacap register in the Quad SPI module.

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