Intel® Arria® 10 Device Datasheet

ID 683771
Date 2/14/2022
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JTAG Configuration Timing

Table 77.  JTAG Timing Parameters and Values for Intel® Arria® 10 Devices
Symbol Description Min Max Unit
tJCP TCK clock period 30, 167 116 ns
tJCH TCK clock high time 14 ns
tJCL TCK clock low time 14 ns
tJPSU (TDI) TDI JTAG port setup time 2 ns
tJPSU (TMS) TMS JTAG port setup time 3 ns
tJPH JTAG port hold time 5 ns
tJPCO JTAG port clock to output 11 ns
tJPZX JTAG port high impedance to valid output 14 ns
tJPXZ JTAG port valid output to high impedance 14 ns
116 The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.