Intel® Arria® 10 Device Datasheet

Download
ID 683771
Date 2/14/2022
Public
Document Table of Contents

Minimum Configuration Time Estimation

Table 86.  Minimum Configuration Time Estimation for Intel® Arria® 10 DevicesThe estimated values are based on the uncompressed configuration bit stream sizes in the Configuration Bit Stream Sizes for Intel® Arria® 10 Devices table
Variant Product Line Active Serial 131 Fast Passive Parallel 132
Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms)
Intel® Arria® 10 GX GX 160 4 100 229.32 32 100 28.67
GX 220 4 100 229.32 32 100 28.67
GX 270 4 100 326.6 32 100 40.82
GX 320 4 100 326.6 32 100 40.82
GX 480 4 100 474.28 32 100 59.28
GX 570 4 100 632.4 32 100 79.05
GX 660 4 100 632.4 32 100 79.05
GX 900 4 100 878.23 32 100 109.78
GX 1150 4 100 878.23 32 100 109.78
Intel® Arria® 10 GT GT 900 4 100 878.23 32 100 109.78
GT 1150 4 100 878.23 32 100 109.78
Intel® Arria® 10 SX SX 160 4 100 229.32 32 100 28.67
SX 220 4 100 229.32 32 100 28.67
SX 270 4 100 326.6 32 100 40.82
SX 320 4 100 326.6 32 100 40.82
SX 480 4 100 474.28 32 100 59.28
SX 570 4 100 632.4 32 100 79.05
SX 660 4 100 632.4 32 100 79.05
131 The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSR may guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table.
132 Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.

Did you find the information on this page useful?

Characters remaining:

Feedback Message