Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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Transceiver Power Supply Operating Conditions

Table 4.  Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GX/SX Devices
Symbol Description Condition 17 Minimum 18 Typical Maximum 18 Unit
VCCT_GXB [L1,R4] [C, D, E, F, G, H, I, J] 19 Transmitter power supply Chip-to-Chip ≤ 17.4 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.0 1.03 1.06 V
Chip-to-Chip ≤ 11.3 Gbps 0.92 0.95 0.98 V
VCCR_GXB[L1,R4] [C, D, E, F, G, H, I, J] 19 Receiver power supply Chip-to-Chip ≤ 17.4 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.0 1.03 1.06 V
Chip-to-Chip ≤ 11.3 Gbps 0.92 0.95 0.98 V
VCCH_GXB[L,R] Transceiver output buffer power supply 1.710 1.8 1.890 V
Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-side basis to minimize power consumption. Refer to the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines and the Intel® Quartus® Prime pin report for information about pinning out the package to minimize power consumption for your specific design.
Table 5.  Transceiver Power Supply Operating Conditions for Intel® Arria® 10 GT Devices
Symbol Description Condition 21 Minimum 18 Typical Maximum 18 Unit
VCCT_GXB[L,R] Transmitter power supply Chip-to-Chip ≤ 25.8 Gbps 22

Or

Backplane 20 ≤ 12.5 Gbps

1.10 1.12 1.14 V
Chip-to-Chip ≤ 15 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.0 1.03 1.06 V
Chip-to-Chip ≤ 11.3 Gbps 0.92 0.95 0.98 V
VCCR_GXB[L,R] Receiver power supply Chip-to-Chip ≤ 25.8 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.10 1.12 1.14 V
Chip-to-Chip ≤ 15 Gbps

Or

Backplane 20 ≤ 12.5 Gbps

1.0 1.03 1.06 V
Chip-to-Chip ≤ 11.3 Gbps 0.92 0.95 0.98 V
VCCH_GXB[L,R] Transceiver output buffer power supply 1.710 1.8 1.890 V
17 These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Intel® Arria® 10 GX/SX Devices for exact data rate ranges.
18 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
19 To support PCIe* Gen3, this pin must be 1.03 V (± 30 mV) or higher.
20 Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.
21 These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Intel® Arria® 10 GT Devices table for exact data rate ranges.
22 25.8 Gbps is the maximum data rate for GT channels. 17.4 Gbps is the maximum data rate for GX channels.

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