Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
SD/MMC Timing Characteristics
|Tsdmmc_cclk||SDMMC_CCLK clock period (Identification mode)||—||2500||—||ns|
|SDMMC_CCLK clock period (Standard SD mode)||—||40||—||ns|
|SDMMC_CCLK clock period (High speed SD mode)||—||20||—||ns|
|Tdutycycle||SDMMC_CCLK duty cycle||45||50||55||%|
|Tsu||SDMMC_CMD/SDMMC_D[7:0] input setup 96||7 – (l4_mp_clk × smplsel/2)||—||—||ns|
|Th||SDMMC_CMD/SDMMC_D[7:0] input hold 96||–2.5 + (l4_mp_clk × smplsel/2)||—||—||ns|
|Td||SDMMC_CMD/SDMMC_D[7:0] output delay 97||–1 + (l4_mp_clk × drvsel/2) 98||—||4 + (l4_mp_clk × drvsel/2) 98||ns|
Figure 11. SD/MMC Timing Diagram
96 When smplsel is set to 2 (in the system manager) and the reference clock (l4_mp_clk) is 200 MHz for example, the setup time is 2 ns and the hold time is 2.5 ns. The Boot ROM uses a smplsel setting of 0 and U-Boot can adjust this setting later in the boot process.
97 When drvsel is set to 3 (in the system manager) and the reference clock (l4_mp_clk) is 200 MHz for example, the output delay time is 6.5 to 11.5 ns. The Boot ROM uses a drvsel setting of 3 and the Intel® Quartus® Prime software can adjust this setting later in the boot process. drvsel set to 0 is not a valid setting.
98 l4_mp_clk is the SD/MMC controller reference clock.
Did you find the information on this page useful?