Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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SD/MMC Timing Characteristics

Table 65.  Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel® Arria® 10 DevicesThese timings apply to SD, MMC, and embedded MMC cards operating at 1.8 V and 3.0 V.
Symbol Description Min Typ Max Unit
Tsdmmc_cclk SDMMC_CCLK clock period (Identification mode) 2500 ns
SDMMC_CCLK clock period (Standard SD mode) 40 ns
SDMMC_CCLK clock period (High speed SD mode) 20 ns
Tdutycycle SDMMC_CCLK duty cycle 45 50 55 %
Tsu SDMMC_CMD/SDMMC_D[7:0] input setup 96 7 – (l4_mp_clk × smplsel/2) ns
Th SDMMC_CMD/SDMMC_D[7:0] input hold 96 –2.5 + (l4_mp_clk × smplsel/2) ns
Td SDMMC_CMD/SDMMC_D[7:0] output delay 97 –1 + (l4_mp_clk × drvsel/2) 98 4 + (l4_mp_clk × drvsel/2) 98 ns
Figure 11. SD/MMC Timing Diagram
96 When smplsel is set to 2 (in the system manager) and the reference clock (l4_mp_clk) is 200 MHz for example, the setup time is 2 ns and the hold time is 2.5 ns. The Boot ROM uses a smplsel setting of 0 and U-Boot can adjust this setting later in the boot process.
97 When drvsel is set to 3 (in the system manager) and the reference clock (l4_mp_clk) is 200 MHz for example, the output delay time is 6.5 to 11.5 ns. The Boot ROM uses a drvsel setting of 3 and the Intel® Quartus® Prime software can adjust this setting later in the boot process. drvsel set to 0 is not a valid setting.
98 l4_mp_clk is the SD/MMC controller reference clock.

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