Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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SPI Timing Characteristics

Table 63.  SPI Master Timing Requirements for Intel® Arria® 10 DevicesYou can adjust the input delay timing by programming the rx_sample_dly register.
Symbol Description Min Typ Max Unit
Tclk SPI_CLK clock period 16.67 ns
Tdutycycle SPI_CLK duty cycle 45 50 55 %
Tdssfrst 91 SPI_SS asserted to first SPI_CLK edge 1.5 × TSPI_CLK – 2 ns
Tdsslst 91 Last SPI_CLK edge to SPI_SS deasserted TSPI_CLK – 2 ns
Tdio Master-out slave-in (MOSI) output delay –1 1 ns
Tsu 92 Input setup in respect to SPI_CLK capture edge 16 – (rx_sample_dly × Tspi_ref_clk) 93 94 ns
Th 92 Input hold in respect to SPI_CLK capture edge 0 ns
Tdssb2b Minimum delay of slave select deassertion between two back-to-back transfers (frames) 1 SPI_CLK
Figure 7. SPI Master Output Timing Diagram
Figure 8. SPI Master Input Timing Diagram
Table 64.  SPI Slave Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Min Typ Max Unit
Tclk SPI_CLK clock period 20 ns
Tdutycycle SPI_CLK duty cycle 45 50 55 %
Ts SPI slave input setup time 5 ns
Th SPI slave input hold time 8 ns
Tsuss SPI_SS asserted to first SCLK_IN edge 5 ns
Thss Last SCLK_IN edge to SPI_SS deasserted 5 ns
Td Master-in slave-out (MISO) output delay 2 × Tspi_ref_clk + 5.3 95 3 × Tspi_ref_clk + 11.8 95 ns
Figure 9. SPI Slave Output Timing Diagram
Figure 10. SPI Slave Input Timing Diagram
91 SPI_SS behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
92 The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.
93 A rx_sample_dly value of 0 is an invalid setting.
94 SPI_REF_CLK is the internal reference clock of the SPI Slave, which is l4_main_clk.
95 SPI_REF_CLK is the internal reference clock of the SPI Slave, which is l4_main_clk.

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