Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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Memory Output Clock Jitter Specifications

Table 55.  Memory Output Clock Jitter Specifications for Intel® Arria® 10 Devices

The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance.

The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.

Protocol Parameter Symbol Non-SmartVID SmartVID (–3V Speed Grade) Unit
Data Rate (Mbps) Min Max Data Rate (Mbps) Min Max
DDR3 Clock period jitter tJIT(per) 2,133 –40 40 1,600 –70 70 ps
Cycle-to-cycle period jitter tJIT(cc) 2,133 –40 40 1,600 –70 70 ps
Duty cycle jitter tJIT(duty) 2,133 –40 40 1,600 –100 100 ps
DDR4 Clock period jitter tJIT(per) 2,400 –40 40 1,600 –63 63 ps
Cycle-to-cycle period jitter tJIT(cc) 2,400 –40 40 1,600 –63 63 ps
Duty cycle jitter tJIT(duty) 2,400 –40 40 1,600 –100 100 ps

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