Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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NAND Timing Characteristics

Table 74.  NAND ONFI 1.0 Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Min Max Unit
tWP 114 Write enable pulse width 10 ns
tWH 114 Write enable hold time 7 ns
tRP 114 Read enable pulse width 10 ns
tREH 114 Read enable hold time 7 ns
tCLS 114 Command latch enable to write enable setup time 10 ns
tCLH 114 Command latch enable to write enable hold time 5 ns
tCS 114 Chip enable to write enable setup time 15 ns
tCH 114 Chip enable to write enable hold time 5 ns
tALS 114 Address latch enable to write enable setup time 10 ns
tALH 114 Address latch enable to write enable hold time 5 ns
tDS 114 Data to write enable setup time 7 ns
tDH 114 Data to write enable hold time 5 ns
tCEA Chip enable to data access time 100 ns
tREA Read enable to data access time 40 ns
tRHZ Read enable to data high impedance 200 ns
tRR Ready to read enable low 20 ns
tWB 114 Write enable high to R/B low 200 ns
Figure 17. NAND Command Latch Timing Diagram
Figure 18. NAND Address Latch Timing Diagram
Figure 19. NAND Data Output Cycle Timing Diagram
Figure 20. NAND Data Input Cycle Timing Diagram
Figure 21. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
Figure 22. NAND Read Status Timing Diagram
Figure 23. NAND Read Status Enhanced Timing Diagram
114 This timing is software programmable.

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