Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
Public
Document Table of Contents

Trace Timing Characteristics

Table 75.  Trace Timing Requirements for Intel® Arria® 10 Devices

To increase the trace bandwidth, Intel recommends routing the trace interface to the FPGA in the HPS Platform Designer (Standard) component. The FPGA trace interface offers a 32-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.

Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed possible. Refer to your trace module datasheet for termination recommendations.

Symbol Description Min Typ Max Unit
Tclk CLK clock period 10 ns
Tdutycycle CLK maximum duty cycle 45 50 55 %
Td CLK to D0–D3 output data delay –0.5 1 ns
Figure 24. Trace Timing Diagram

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