Intel® Arria® 10 Device Datasheet

ID 683771
Date 2/14/2022
Public
Document Table of Contents

HPS PLL Output Specifications

Table 61.  HPS PLL Output Specifications for Intel® Arria® 10 Devices
Description Min Max Max Unit
Clock jitter tolerance –2.5 2.5 %
Clock duty cycle 45 50 55 %
Clock rise time 350 1075 ps
Clock fall time 200 450 ps
HPS PLL lock time 3.6 ms