AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
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1.4. Evaluating Data Setup and Hold Timing Slack

In AS configuration scheme, the FPGA will initiate the configuration process after POR. During the configuration process, the FPGA issues flash operation commands such as read device ID, normal read and erase bulk. You must ensure that the FPGA is able to read the data correctly from the configuration devices. This is done by ensuring the setup time, tDSU and hold time, tDH meets the requirements explained in the respective FPGA device datasheets. To evaluate the tDSU and tDH in your system, follow the guideline below.

Figure 7. FPGA to EPCQ-A Board Trace Block DiagramOther type of configuration device or flash is supported by the FPGA.

The data setup timing slack must be equal or larger than the minimum data setup time, tDSU

tDCLK – (tBT_DCLK + tCLQV + tBT_DATA) ≥ tDSU

The hold timing slack must be equal or larger than the minimum data hold time, tDH:

tBT_DCLK + tCLQX + tBT_DATA ≥ tDH

  • tDCLK = Period for a DCLK cycle
  • tBT_DCLK = Board trace propagation delay for DCLK from FPGA to EPCQ-A
  • tCLQV = Clock low to output valid
  • tCLQX = Output hold time
  • tBT_DATA = Board trace propagation delay for Data from EPCQ-A to FPGA
  • tDSU = Minimum data setup time required by FPGA
  • tDH = Minimum data hold time required by FPGA

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