AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
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1.5.1.3. Example for Adding Buffer on the DCLK

The following two simulation setups are used to measure the minimum or maximum delay on the DCLK signal.

Figure 20. Simulation Setup with the Default Load on the DCLK Signal
Figure 21. Simulation Setup with the Actual System Load on the DCLK SignalBuffer model must be included.
Figure 22. Minimum DCLK Delay for Delay Measurements A and C
Figure 23. Minimum DCLK Delay for Delay Measurements B and D

The minimum DCLK delay is shown in the following equation.

Minimum DCLK delay = (delay measurement C – delay measurement A) + [minimum buffer delay + (delay measurement D – delay measurement B)]

Minimum DCLK delay = –0.080ns + 1.8ns28 – 0.0425ns

Minimum DCLK delay = 1.677ns

Figure 24. Maximum DCLK Delay for Delay Measurements A and C
Figure 25. Maximum DCLK Delay for Delay Measurements B and D

The maximum DCLK delay is shown in the following equation.

Maximum DCLK delay = (delay measurement C – delay measurement A) + [maximum buffer delay + (delay measurement D – delay measurement B)]

Maximum DCLK delay = –0.371ns + 5.7ns29 – 0.137ns

Maximum DCLK delay = 5.191ns

28 The minimum buffer delay specification is 1.8ns at 15pF loading.
29 The maximum buffer delay specification is 5.7ns at 15pF loading.

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