AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.5.1.3. Example for Adding Buffer on the DCLK

The following two simulation setups are used to measure the minimum or maximum delay on the DCLK signal.

Figure 20. Simulation Setup with the Default Load on the DCLK Signal
Figure 21. Simulation Setup with the Actual System Load on the DCLK SignalBuffer model must be included.
Figure 22. Minimum DCLK Delay for Delay Measurements A and C
Figure 23. Minimum DCLK Delay for Delay Measurements B and D

The minimum DCLK delay is shown in the following equation.

Minimum DCLK delay = (delay measurement C – delay measurement A) + [minimum buffer delay + (delay measurement D – delay measurement B)]

Minimum DCLK delay = –0.080ns + 1.8ns28 – 0.0425ns

Minimum DCLK delay = 1.677ns

Figure 24. Maximum DCLK Delay for Delay Measurements A and C
Figure 25. Maximum DCLK Delay for Delay Measurements B and D

The maximum DCLK delay is shown in the following equation.

Maximum DCLK delay = (delay measurement C – delay measurement A) + [maximum buffer delay + (delay measurement D – delay measurement B)]

Maximum DCLK delay = –0.371ns + 5.7ns29 – 0.137ns

Maximum DCLK delay = 5.191ns


Section Content
Simulation Results

28 The minimum buffer delay specification is 1.8ns at 15pF loading.
29 The maximum buffer delay specification is 5.7ns at 15pF loading.
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