AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline

Document Version Changes
2020.04.29 Updated the unit for resistance to mΩ in the RLC Value Used for the DCLK and DATA Pins table.
2020.04.16 Updated the reference to the IBIS Models for Intel® Devices in the Cyclone® V to Cyclone® V QS Device Migration Reference Manual section.
2020.04.10
  • Added the Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V section.
  • Added the Board Design Guidelines for Cyclone® V to Cyclone® V QS Device Migration section.
  • Added reference to How can I use EPCQ-A Serial Configuration Devices in ASMI Parallel II Intel® FPGA IP when using Intel® Quartus® Prime Standard Edition software version 17.0.2 and earlier? in the Software Support for EPCQ-A Devices section.
2019.10.17
  • Added a note to the minimum value of the EPCQ and EPCQ-A devices of the VIH parameter in the EPCS, EPCQ and EPCQ-A Devices Operating Conditions table.
  • Added a note about compression and encryption in the Programming File Compatibility section.
  • Added a note about using the 13.1.4 patch 4.70r in the Software Migration Guidelines section.
  • Updated the package dimensions in the following tables:
    • Package Dimension Comparison for 8-Pin SOIC Package Devices table
    • Package Dimension Comparison for 16-Pin SOIC Package Devices table
  • Updated the minimum value of the VIH parameter for EPCS in the EPCS, EPCQ and EPCQ-A Devices Operating Conditions table.
2018.03.30
  • Updated EPCQA instances to EPCQ-A.
  • Added a note and updated the compatibility conditions in Programming File Compatibility Guide table.
  • Updated document title from AN 822: Intel® Configuration Device Migration Guideline to AN 822: Intel® FPGA Configuration Device Migration Guideline.
  • Removed Preliminary tag for EPCS to EPCQ-A Device Migration IP Core Compatibility and EPCQ to EPCQ-A Device Migration IP Core Compatibility tables.
Date Version Changes
January 2018 2018.01.11 Edited the 2.5V I/O note in EPCS, EPCQ and EPCQA Devices Operating Conditions table.
December 2017 2017.12.15 Updated t nCLK2D / tCLQV for EPCQA device in EPCS and EPCQA Devices Read Operation Timing Parameters table.
August 2017 2017.08.14
  • Updated Pin 1 in 16-pin SOIC Device Pin Information.
  • Updated condition for Low-level output voltage in EPCS, EPCQ and EPCQA Devices Operating Conditions.
August 2017 2017.08.04 Updated minimum value for Low-level output voltage in EPCS, EPCQ and EPCQA Device Operating Conditions.
August 2017 2017.08.02 Initial release.
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