AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
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1.5.1.2.2. Example for Simulating the DATA Link

The following three simulation setups are essential to measure the minimum or maximum delay on the DATA signal.

Figure 14. Simulation Setup with the Default Maximum Load on the DATA Signal
  • The setup is used to measure the maximum delay on the DATA signal.
  • The maximum flash clock to output delay (tCLQV ) value in the EPCQ-A Serial Configuration Device Datasheet is based on 30pF loading.
Figure 15. Simulation Setup with the Default Minimum Load on the DATA Signal
  • The setup is used to measure the minimum delay on the DATA signal.
  • The minimum flash clock to output delay (tCLQX ) value in the EPCQ-A Serial Configuration Device Datasheet is based on 0pF loading.
Figure 16. Simulation Setup with the Actual System Load on the DATA Signal
Figure 17. Maximum DATA Delay

The maximum DATA delay is calculated by substituting the delay measured between E and C in the simulation into the following equation.

Maximum DATA delay = tCLQV + (delay measurement Edelay measurement C)

Maximum DATA delay = 6ns2.343ns

Maximum DATA delay = 3.657ns

The results clearly show that the maximum DATA delay could be smaller depending on the actual system loading which helps to improve the FPGA setup time slack. Using the tCLQV value defined in the EPCQ-A Serial Configuration Device Datasheet is too pessimistic in the setup time analysis.

Figure 18. Minimum DATA Delay

The minimum DATA delay is calculated by substituting the delay measured between E and D in the simulation into the following equation.

Minimum DATA delay = tCLQX + (delay measurement Edelay measurement D)

Minimum DATA delay = 1.5ns + 0.542ns

Minimum DATA delay = 2.042ns

The results clearly show that the minimum DATA delay could be larger depending on the actual system loading. Using the tCLQX value defined in the EPCQ-A Serial Configuration Device Datasheet is too pessimistic for the hold time analysis.

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