ID 683340
Date 4/29/2020
Public

## 1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme

The board design guidelines provide recommendation on how to add extra delay on DCLK or DATA signals via trace length, resistor-capacitor (RC) network, or buffer to meet the FPGA hold time (tDH) and setup time (tDSU) specification for DCLK running at 50 MHz or lower and 100 MHz. The additional delay helps to improve the hold timing slack of the AS configuration scheme.

The following are the board design guidelines for DCLK running at 50 MHz or lower use case and 100 MHz use case. The recommendations are applicable for migrating from an existing EPCQ device or a third-party serial flash device to the EPCQ-A device or a faster third-party serial flash device.

Table 21.  Configuration Device Migration Recommendations
Supporting DCLK at 50-MHz or Lower Operation Supporting DCLK at 100-MHz Operation
Recommendation 1—Add an extra RC network on the DCLK line near flash end.

You must design the board trace for the DCLK and DATA with the following recommendation to meet the timing requirement for the FPGA and the EPCQ-A device.

You can use the data setup or hold timing equations to identify the range for the minimum and maximum delays. The range is essential to be used as a reference to ensure the total propagation delay for the DCLK and DATA signals must be designed within the range.

Recommendation 2—Add an extra buffer on the DCLK line between the FPGA and the serial flash device.

The equations to analyze the setup or hold time can be used to calculate the extra delay by using the RC network or buffer on the DCLK signal is needed to ensure it meets the FPGA tDH and tDSU specifications. The following example shows you how to calculate the extra delay.

### Calculating the Extra Delay

• Assumption for the system setup:
• DCLK frequency: 50MHz (Period 20ns)
• Cyclone® V AS timing specifications:
• Minimum tDSU : 1.5ns
• Minimum tDH : 2.9ns
• Intel® EPCQ64ASI16N flash specifications:
• tCLQV : 6ns
• tCLQX : 1.5ns
• To identify the allowed maximum extra delay:
tDCLK - (tBT_DCLK + tCLQV + tBT_DATAmax) ≥ tDSU
= (tBT_DCLK + tBT_DATAmax) ≤ tDCLK - tCLQV - tDSU
= (tBT_DCLK + tBT_DATAmax) ≤ 20ns - 6ns - 1.5ns
= (tBT_DCLK + tBT_DATAmax) ≤ 12.5ns

The allowed maximum extra delay is 12.5ns.

• To identify the required minimum extra delay:
tBT_DCLK + tCLQX + tBT_DATAmin ≥ tDH
= tBT_DCLK + tBT_DATAmin ≥ tDH - tCLQX
= tBT_DCLK + tBT_DATAmin ≥ 2.9ns - 1.5ns
= tBT_DCLK + tBT_DATAmin ≥ 1.4ns

The required minimum delay is 1.4ns.

As a conclusion, the extra delay added must fall within the calculated range to meet the required FPGA data hold time (tDH) while not violating the data setup time (tDSU) specification.