AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example IBIS Simulation Setup for Arria® V, Cyclone® V, and Stratix® V Devices 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.5.1.1. IBIS Simulation Example

In this board design guidelines, the following IBIS simulation was performed to provide recommendation on the topology to estimate the minimum and maximum delays that can be achieved on the DCLK and DATA signals.

The FPGA26 and EPCQ-A IBIS models are used in the following IBIS simulation example by adding extra RC network or buffer on the DCLK signal. The simulation result is used to ensure the delay added on the DCLK is sufficient to meet the actual FPGA tDH and tDSU specifications and ensure the signal quality is good.

IBIS Simulation Setup for Arria® V, Cyclone® V, and Stratix® V Devices

  • Cyclone® V LVTTL-3.0V I/O model is used in the IBIS simulation example shown below
    • DCLK: lvttl30_ctnio_d12s1
    • DATA: lvttl30_ctnio_d8s1
  • Arria® V LVTTL-3.0V I/O model
    • DCLK: lvttl30_ctio_d12s1
    • DATA: lvttl30_ctio_d8s1
  • Stratix® V LVTTL-3.3V I/O model
    • DCLK: lvttl_ctnio_d12s1
    • DATA: lvttl_ctnio_d8s1
  • Table 22.  RLC Value Used for the DCLK and DATA PinsThe RLC value could be varied depending on the package size.
    Pin Name R (mΩ) L (nH) C (pF)
    DCLK 252.71 2.26 1.07
    DATA 633.45 5.61 1.74
  • Intel® EPCQ64ASI16N model is used
  • VCC at 3.3V ±5% is used for both the FPGA and flash devices
  • One inch trace with 50Ω trace impedance on the typical FR4 board is used
  • Simulation is done on both the Slow and Fast IC corners

In addition, Hyperlynx IBIS simulation is used to predict the effects of a given link. The delay of a given link can be estimated accurately using the technique of comparing the simulated delay between the default setup (Configuration 1) and the actual system setup (Configuration 2) as shown in the figure below. The actual use of this methodology to measure the AS configuration timing are performed in the following section.

Figure 8. Simulated Delay Comparison
Note: When measuring the delay of a signal at 50% of the voltage level as shown in the figure below, the IBIS simulation was performed by measuring the voltage at 50% of the voltage level. You can measure at the voltage input high (VIH ) or voltage input low (VIL ) level.
Figure 9. Voltage Level Delay Measurement
26 The Cyclone® V FPGA is used in the following IBIS simulation example.
Level Two Title