220.127.116.11. IBIS Simulation Example
In this board design guidelines, the following IBIS simulation was performed to provide recommendation on the topology to estimate the minimum and maximum delays that can be achieved on the DCLK and DATA signals.
The FPGA26 and EPCQ-A IBIS models are used in the following IBIS simulation example by adding extra RC network or buffer on the DCLK signal. The simulation result is used to ensure the delay added on the DCLK is sufficient to meet the actual FPGA tDH and tDSU specifications and ensure the signal quality is good.
IBIS Simulation Setup for Arria® V, Cyclone® V, and Stratix® V Devices
- Cyclone® V LVTTL-3.0V I/O model is used in the IBIS simulation example shown below
- DCLK: lvttl30_ctnio_d12s1
- DATA: lvttl30_ctnio_d8s1
- Arria® V LVTTL-3.0V I/O model
- DCLK: lvttl30_ctio_d12s1
- DATA: lvttl30_ctio_d8s1
- Stratix® V LVTTL-3.3V I/O model
- DCLK: lvttl_ctnio_d12s1
- DATA: lvttl_ctnio_d8s1
Table 22. RLC Value Used for the DCLK and DATA PinsThe RLC value could be varied depending on the package size. Pin Name R (mΩ) L (nH) C (pF) DCLK 252.71 2.26 1.07 DATA 633.45 5.61 1.74
- Intel® EPCQ64ASI16N model is used
- VCC at 3.3V ±5% is used for both the FPGA and flash devices
- One inch trace with 50Ω trace impedance on the typical FR4 board is used
- Simulation is done on both the Slow and Fast IC corners
In addition, Hyperlynx IBIS simulation is used to predict the effects of a given link. The delay of a given link can be estimated accurately using the technique of comparing the simulated delay between the default setup (Configuration 1) and the actual system setup (Configuration 2) as shown in the figure below. The actual use of this methodology to measure the AS configuration timing are performed in the following section.
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