AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
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1.5.1.2.3. Simulation Results

The following table shows the minimum and maximum delays on the DCLK and DATA links can be obtained accurately via the IBIS simulation.

Table 23.  Minimum and Maximum Delays on the DCLK and DATA Links
Signal IC Corner Total Delay Measured via IBIS Simulation at VCC/2 (ns)27 Notes
DCLK Fast/Strong 2.514 Minimum DCLK delay
DCLK Slow/Weak 3.886 Maximum DCLK delay
DATA Fast/Strong 2.042 Minimum DATA delay
DATA Slow/Weak 3.657 Maximum DATA delay

Ultimately, the data setup time slack and the data hold time slack can be obtained by substituting the delay obtained from the IBIS simulation in the following equations.

Assumption for the system setup:

  • DCLK frequency: 50MHz (period 20ns)
  • Cyclone® V AS timing specifications:
    • Minimum tDSU : 1.5ns
    • Minimum tDH : 2.9ns

This equation shows the data setup time slack calculation.

Data setup time slack = tDCLK tDSU – (maximum DCLK delay + maximum DATA delay)

Data setup time slack = 20ns – 1.5ns – (3.886ns + 3.657ns)

Data setup time slack = 10.957ns

This equation shows the data hold time slack calculation.

Data hold time slack = (Minimum DCLK delay + minimum DATA delay) – tDH

Data hold time slack = (2.514ns + 2.042ns) – 2.9ns

Data hold time slack = 1.656ns

The DCLK signal quality is good with the extra RC network as shown in the simulation waveform below. The DCLK signal is simulated using 50 Mbps clock pattern.

Figure 19. Simulating the DCLK Signal at 50 Mbps Operation

By adding the recommended RC network, the DCLK and DATA trace lengths can be designed to as short as possible and are able to meet the minimum data setup or hold time required by the Cyclone® V FPGA.

A smaller maximum DATA delay can be obtained via the simulation technique. The FPGA AS configuration data setup time slack can be improved with the simulation value compared to the flash datasheet specifications.

A larger minimum DATA delay can be obtained via the simulation technique. The FPGA AS configuration data hold time slack can be improved with simulation value compared to the flash datasheet specifications.

27 The data listed is based on the manual measurement from the simulation waveform.

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