AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents

1.3.2.1. Read Operation Timing

Table 6.  EPCS and EPCQ-A Devices Read Operation Timing Parameters
Symbol Parameter Capacity Min Max Unit
EPCS EPCQ-A EPCS EPCQ-A
f RCLK Read clock frequency All 20 50 MHz
Fast read clock frequency All 40 100 MHz
t CH DCLK high time 4 Mb 11 4 or 6 14 ns
All others 11 3.4 or 9 15
t CL DCLK low time 4Mb 11 4 or 614 ns
All others 11 3.4 or 915
t ODIS Output disable time after read All 8 7 ns
t nCLK2D / tCLQV 16 Clock falling edge to DATA 4Mb 8 8 ns
All others 8 6
Table 7.  EPCQ and EPCQ-A Devices Read Operation Timing Parameters
Symbol Parameter Capacity Min Max Unit
EPCQ EPCQ-A EPCQ EPCQ-A
f RCLK Read clock frequency All 50 50 MHz
Fast read clock frequency All 100 100 MHz
t CH DCLK high time All 4 3.4 or 915 ns
t CL DCLK low time All 4 3.4 or 915 ns
t ODIS Output disable time after read All 8 7 ns
t nCLK2D / tCLQV 16 Clock falling edge to DATA All 7 6 ns
14 4 ns is for normal read and 6 ns is for fast read.
15 3.4 ns is for normal read and 9 ns is for fast read.
16 t nCLK2D is used in EPCS and EPCQ devices while tCLQV is used in EPCQ-A devices.

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