AN 822: Intel® FPGA Configuration Device Migration Guideline

Download PDF
ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.3.2.1. Read Operation Timing

Table 6.  EPCS and EPCQ-A Devices Read Operation Timing Parameters
Symbol Parameter Capacity Min Max Unit
EPCS EPCQ-A EPCS EPCQ-A
f RCLK Read clock frequency All — — 20 50 MHz
Fast read clock frequency All — — 40 100 MHz
t CH DCLK high time 4 Mb 11 4 or 6 14 — — ns
All others 11 3.4 or 9 15 — —
t CL DCLK low time 4Mb 11 4 or 614 — — ns
All others 11 3.4 or 915 — —
t ODIS Output disable time after read All — — 8 7 ns
t nCLK2D / tCLQV 16 Clock falling edge to DATA 4Mb — — 8 8 ns
All others — — 8 6
Table 7.  EPCQ and EPCQ-A Devices Read Operation Timing Parameters
Symbol Parameter Capacity Min Max Unit
EPCQ EPCQ-A EPCQ EPCQ-A
f RCLK Read clock frequency All — — 50 50 MHz
Fast read clock frequency All — — 100 100 MHz
t CH DCLK high time All 4 3.4 or 915 — — ns
t CL DCLK low time All 4 3.4 or 915 — — ns
t ODIS Output disable time after read All — — 8 7 ns
t nCLK2D / tCLQV 16 Clock falling edge to DATA All — — 7 6 ns
14 4 ns is for normal read and 6 ns is for fast read.
15 3.4 ns is for normal read and 9 ns is for fast read.
16 t nCLK2D is used in EPCS and EPCQ devices while tCLQV is used in EPCQ-A devices.
Level Two Title