AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
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1.5.1.3.1. Simulation Results

The following table shows the minimum and maximum delays that can be obtained from the type of buffer used in this example.

Table 24.  Minimum and Maximum DCLK Delays
  • The data listed is based on the manual measurement from the simulation waveform.
  • The EPCQ-A device DCLK loading is 6pF, a 9pF capacitive load is added in the simulation setup to match the expected output loading of the buffer specification.
IC Corner Output Loading, CL (pF) Cyclone® V DCLK to Buffer Delay (ns) Buffer to EPCQ-A DCLK Delay (ns) Total DCLK Delay at VCC/2 (ns) Notes
Fast/Strong 15 –0.080 1.757 1.677 Minimum DCLK delay
Slow/Weak 15 –0.371 5.562 5.191 Maximum DCLK delay

Ultimately, the data setup time slack and the data hold time slack can be obtained by substituting the delay obtained from the IBIS simulation in the following equations.

Assumption for the system setup:

  • DCLK frequency: 50MHz (period 20ns)
  • Cyclone® V AS timing specifications:
    • Minimum tDSU : 1.5ns
    • Minimum tDH : 2.9ns

This equation shows the data setup time slack calculation.

Data setup time slack = tDCLK tDSU – (maximum DCLK delay + maximum DATA delay)

Data setup time slack = 20ns – 1.5ns – (5.191ns + 3.657ns)

Data setup time slack = 9.652ns

This equation shows the data hold time slack calculation.

Data hold time slack = (Minimum DCLK delay + minimum DATA delay) – tDH

Data hold time slack = (1.677ns + 2.042ns) – 2.9ns

Data hold time slack = 0.819ns

The DCLK signal quality is good with the extra buffer as shown in the simulation waveform below. The DCLK signal is simulated using 50 Mbps clock pattern.

Figure 26. Simulation Results for Cyclone® V FPGA-to-Buffer
Figure 27. Simulation Results for Buffer-to-EPCQ-A Device

You can select any buffer in the market as long as the total delay for buffer, DCLK, and DATA is meeting the FPGA tDSU and tDH and the EPCQ-A setup and hold timing requirements.

By adding buffer, the DCLK and DATA trace lengths can be designed to as short as possible. The additional delay obtained from buffer, including other timing components help to meet the minimum data setup and hold time required by the Cyclone® V FPGA.

Note: You need to add the appropriate capacitive load on the DCLK line. For more details, refer to the buffer's data sheet. Adding the capacitive load is essential to obtain the desired delay from the buffer. You must take the EPCQ-A or the third-party flash input pin capacitance into consideration to determine the additional capacitive load value.

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