AN 822: Intel® FPGA Configuration Device Migration Guideline

ID 683340
Date 4/29/2020
Public
Document Table of Contents
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1.3.2.2. Write Operation Timing

Table 8.  EPCS and EPCQ-A Devices Write Operation Timing Parameters
Symbol Operation Capacity Min Typical Max Unit
EPCS EPCQ-A EPCS EPCQ-A EPCS EPCQ-A
f WCLK Write clock frequency All 25 100 MHz
t CH DCLK high 4 20 4 ns
All others 20 3.4
t CL DCLK low 4 20 4 ns
All others 20 4
t NCSSU Chip select ( nCS ) setup All 10 5 ns
t NCSH Chip select ( nCS ) hold All 10 5 ns
t DSU DATA[] in setup before DCLK rising edge All 5 2 ns
t DH DATA[] hold time after DCLK rising edge 4 5 5 ns
All others 5 3
t CSH Chip select ( nCS ) high 4 100 100 ns
All others 100 10 / 5017
t WB Write bytes cycle 1 1.5 5 ms
4 1.5 0.4 5 0.8 ms
16 1.5 0.4 5 3 ms
32 0.7 3 ms
64 1.5 0.8 5 3 ms
128 2.5 0.7 7 3 ms
t WS Write status cycle All 5 10 15 15 ms
t EB Erase bulk cycle 1 3 6 s
4 5 1 10 4 s
16 17 5 40 25 s
32 10 50 s
64 68 20 160 100 s
128 105 40 250 200 s
t ES Erase sector cycle 4 2 0.15 3 1 s
All others 2 0.15 3 2 s
Table 9.  EPCQ and EPCQ-A Devices Write Operation Timing Parameters
Symbol Operation Capacity Min Typical Max Unit
EPCQ EPCQ-A EPCQ EPCQ-A EPCQ EPCQ-A
f WCLK Write clock frequency All 100 100 MHz
t CH DCLK high All 4 3.4 ns
t CL DCLK low All 4 4 ns
t NCSSU Chip select ( nCS ) setup All 4 5 ns
t NCSH Chip select ( nCS ) hold All 4 5 ns
t DSU DATA[] in setup before DCLK rising edge All 2 2 ns
t DH DATA[] hold time after DCLK rising edge All 3 3 ns
t CSH Chip select ( nCS ) high All 50 10 / 5018 ns
t WB Write bytes cycle 16 0.6 0.4 5 3 ms
32 0.6 0.7 5 3 ms
64 0.6 0.8 5 3 ms
128 0.6 0.7 5 3 ms
t WS Write status cycle All 1.3 10 8 15 ms
t EB Erase bulk cycle 16 30 5 60 25 s
32 30 10 60 50 s
64 60 20 250 100 s
128 170 40 250 200 s
t ES Erase sector cycle All others 0.7 0.15 3 2 s
128 0.7 0.15 6 2 s
17 10ns for read and 50 ns for erase program and write.
18 10ns for read and 50 ns for erase program and write.