AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.3.6.1. Sector Protect

Table 16.  Sector Protect Comparison for EPCS4 and EPCQ4A Devices
Note: Set TB bit to 0 for backward compatibility.
Status Register EPCS4 EPCQ4A
TB BP2 BP1 BP0 Protected Sectors (8 sectors)
x 0 0 0 None None
0 0 0 1 7 7
0 0 1 0 6-7 6-7
0 0 1 1 4-7 4-7
1 0 0 1 N/A 0
1 0 1 0 N/A 0-1
1 0 1 1 N/A 0-3
x 1 x x All All
Table 17.  Sector Protect Comparison for EPCS16, EPCQ16 and EPCQ16A Devices
Note: Set TB bit to 0 for backward compatibility for migration from EPCS16.
Status Register EPCS16 EPCQ16 EPCQ16A
TB BP2 BP1 BP0 Protected Sectors (32 sectors)
0 0 0 0 None None None
0 0 0 1 31 31 31
0 0 1 0 30-31 30-31 30-31
0 0 1 1 28-31 28-31 28-31
0 1 0 0 24-31 24-31 24-31
0 1 0 1 16-31 16-31 16-31
0 1 1 0 All All All
0 1 1 1 All All All
1 0 0 0 N/A None None
1 0 0 1 N/A 0 0
1 0 1 0 N/A 0-1 0-1
1 0 1 1 N/A 0-3 0-3
1 1 0 0 N/A 0-7 0-7
1 1 0 1 N/A 0-15 0-15
1 1 1 0 N/A All All
1 1 1 1 N/A All All
Table 18.  Sector Protect Comparison for EPCQ32 and EPCQ32A Devices
Status Register EPCQ32 EPCQ32A
TB BP2 BP1 BP0 Protected Sectors (64 sectors)
0 0 0 0 None None
0 0 0 1 63 63
0 0 1 0 62-63 62-63
0 0 1 1 60-63 60-63
0 1 0 0 56-63 56-63
0 1 0 1 48-63 48-63
0 1 1 0 32-63 32-63
0 1 1 1 All All
1 0 0 0 None None
1 0 0 1 0 0
1 0 1 0 0-1 0-1
1 0 1 1 0-3 0-3
1 1 0 0 0-7 0-7
1 1 0 1 0-15 0-15
1 1 1 0 0-31 0-31
1 1 1 1 All All
Table 19.  Sector Protect Comparison for EPCS64, EPCQ64 and EPCQ64A Devices
Note: Set TB bit to 0 for backward compatibility for migration from EPCS64.
Status Register EPCS64 EPCQ64 EPCQ64A
TB BP2 BP1 BP0 Protected Sectors (128 sectors)
0 0 0 0 None None None
0 0 0 1 126-127 127 126-127
0 0 1 0 124-127 126-127 124-127
0 0 1 1 120-127 124-127 120-127
0 1 0 0 112-127 120-127 112-127
0 1 0 1 96-127 112-127 96-127
0 1 1 0 64-127 96-127 64-127
0 1 1 1 All 64-127 All
1 0 0 0 N/A None None
1 0 0 1 N/A 0 0-1
1 0 1 0 N/A 0-1 0-3
1 0 1 1 N/A 0-3 0-7
1 1 0 0 N/A 0-7 0-15
1 1 0 1 N/A 0-15 0-31
1 1 1 0 N/A 0-31 0-63
1 1 1 1 N/A 0-63 All
Table 20.  Sector Protect Comparison for EPCS128, EPCQ128 and EPCQ128A Devices
Status Register EPCS12824 EPCQ128 25 EPCQ128A25
TB BP2 BP1 BP0 Protected Sectors (64 sectors)
0 0 0 0 None None None
0 0 0 1 63 255 252-255
0 0 1 0 62-63 254-255 248-255
0 0 1 1 60-63 252-255 240-255
0 1 0 0 56-63 248-255 224-255
0 1 0 1 48-63 240-255 192-255
0 1 1 0 32-63 224-255 128-255
0 1 1 1 All 192-255 All
1 0 0 0 N/A None None
1 0 0 1 N/A 0 0-3
1 0 1 0 N/A 0-1 0-7
1 0 1 1 N/A 0-3 0-15
1 1 0 0 N/A 0-7 0-31
1 1 0 1 N/A 0-15 0-63
1 1 1 0 N/A 0-31 0-127
1 1 1 1 N/A 0-63 All
24 262144 byte (2MB) per sector
25 65536 byte (512KB) per sector
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