AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
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1.5.1.2.1. Example for Simulating the DCLK Link

The following two simulation setups are used to measure the minimum or maximum delay on the DCLK signal.

Figure 10. Simulation Setup with the Default Load on the DCLK SignalYou must follow the recommended default load setup.
Figure 11. Simulation Setup with the Actual System Load including the RC Network Solution on the DCLK SignalThe RC network must be included.

By running simulation on both slow and fast corners, the minimum and maximum delays on the DCLK can be measured by comparing the delay measured between A and B.

Figure 12. Minimum DCLK Delay
Figure 13. Maximum DCLK Delay

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