AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.2.2. Programming File Compatibility

Note: This section describes programming file compatibility for designs without Intel® FPGA IP cores.

List of supported programming files:

  • Programmer Object File (.pof)
  • JTAG Indirect Configuration File (.jic)
  • Raw Programming Data (.rpd)
  • STAPL File (.jam/.jbc)
  • Serial Vector Format (.svf)
Note: Compression and encryption would not affect the programming file compatibility.
Table 3.  Programming File Compatibility Guide
Note: For designs that do not contain IP cores which interface with the configuration device, depending upon the FPGA family and configuration scheme implemented, the existing programming files may be compatible with EPCQ-A devices without the need to regenerate the programming files.
Device Family Original Configuration Device Configuration Device Density Programming Files supported Disable EPCS/EPCQ ID check Setting Compatible with EPCQ-A2 3
Legacy FPGA devices EPCS 64Mb & below .pof/.jic/.rpd/.jam/.jbc Any Yes
.svf Any Yes 4
128Mb .pof/.jic/.rpd Any Yes 5
.svf Any Yes4
.jam/.jbc Any No 6
EPCQ Any .pof/.jic/.rpd/.jam/.jbc On 7 Yes
.svf On7 Yes4
Cyclone® V, Arria® V, and Stratix® V devices EPCS 64Mb & below .pof/.jic/.rpd/.jam/.jbc On 8 Yes
.svf On8 Yes4
128Mb .pof/.jic/.rpd On8 Yes5
.svf On8 Yes4
.jam/.jbc Any No6
EPCQ9 Any Any Any No

Refer to IP Core and Programming File Migration Guideline for more information about guidelines on incompatible programming files.

2 Table assumes other compatibility considerations are satisfied.
3 Table assumes the programming files do not contain any ASMI Parallel IP or Serial Flash Loader IP.
4 Only supported for .svf files generated for EPCS devices to be used to program an EPCQ-A, and not the other way round.
5 In .rpd file, the binary data is the same between EPCS128 and EPCQ128A. However due to different sector size, a proper erasing procedure is required when programming each device.
6 Due to different sector size, the .jam/.jbc file is different between EPCS and EPCQ.
7 In Intel® Quartus® Prime version 15.1 or later, automatic mode turns on this option automatically.
8 Other than Intel® Quartus® Prime version 13.0 to 15.0, automatic mode turns on this option automatically.
9 EPCQ programming files are not compatible with EPCQ-A in AS x1 or AS x4 modes.
Level Two Title