1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
18.104.22.168. Simulating the DCLK Signal at 100 MHz Operation
Example to add the RC network or buffer solution is not applicable to the 100 MHz operation because the additional delay uncertainty imposed by the RC network or buffer can cause setup time violation on the FPGA.
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