AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents

1.3.6. Status Register

Table 15.  Status Register Bits for EPCS, EPCQ and EPCQ-A Devices
Bit Name Description R/W EPCS EPCQ EPCQ-A
1 4/16/64/128 16/32 64/128 All
7 RSV Reserved
6 BP323 Block Protect Bit 3 R/W No No No Yes No
5 TB Top/Bottom Bit R/W No No Yes Yes Yes
4 BP2 Block Protect Bit 2 R/W No Yes Yes Yes Yes
3 BP1 Block Protect Bit 1 R/W Yes Yes Yes Yes Yes
2 BP0 Block Protect Bit 0 R/W Yes Yes Yes Yes Yes
1 WEL Write Enable Latch R Yes Yes Yes Yes Yes
0 WIP Write In Progress R Yes Yes Yes Yes Yes
23 This is a reserved bit in EPCQ-A device and must be set to 0.

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