1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2.3. IP Core and Programming File Migration Guideline
Note: This section describes programming file compatibility for designs with Intel® FPGA IP cores that interface with the configuration device.
Refer to the following diagram to determine the subsequent tasks and guidelines for migration:
- IP core and programming file are incompatible—regenerate IP core and programming file shown in IP Core Regeneration Guideline.
- Programming file is incompatible—regenerate programming file shown in Programming File Regeneration Guideline.
- IP core and programming file are compatible—no additional task required and you can reuse the existing programming file.
Figure 2. IP Core and Programming File Compatibility Flow Chart
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