How can I avoid common mistakes when implementing Altera® FPGA configuration schemes?

All Altera® FPGAs need to be configured with a user image to perform the desired user function.  

Depending on the device family, Altera FPGAs support different configuration modes and have different architectures and requirements to facilitate successful configuration.

Since it is imperative to mitigate against configuration failures when designing the target board, this KDB lists some mistakes commonly made when implementing a configuration scheme with Altera FPGAs, which may result in configuration failures.

Cyclone® 10 FPGAs, Arria® 10 FPGAs, and earlier devices

Device families in this category employ a state-machine-based architecture for configuration control and processing, with dedicated and dual-purpose configuration pins. Below is a list of common mistakes made with these device families that could result in configuration failure.

Incorrect or missing pull-up resistors on Open-Drain configuration pins

Altera provides recommended values for pull-up resistors for configuration pins based on device characterization, which should be adhered to. Some configuration pins (nSTATUS, CONF_DONE, INIT_DONE, etc) are implemented as Open-Drain and thus a pull-up of 10-K Ohms is mandatory such that they can drive a logic high when released by the FPGA.

Dedicated or dual-purpose configuration pins are inadvertently left unconnected

Dual-purpose Configuration Pins enabled in the Quartus® Prime Software project should not be left N/C on the target device and board. For example, if INIT_DONE is enabled in the project and not pulled high on the board, the device may not enter user mode after configuration completes. Check your Quartus® Prime Software project settings file (.qsf) to determine which options have been enabled.

Excessive load on CONF_DONE

When using Active Serial configuration mode, configuration success may be sensitive to the rise time of CONF_DONE. To prevent this, excessive load should not be connected to this pin, and if driving an LED, this should be done via a field-effect transistor (FET) or buffer.

See:

• Can loading on the CONF_DONE line result in configuration failure from my configuration device?

Circuitry or buffers placed between the FPGA AS pins and QSPI devices

It is generally not recommended to place voltage translators or buffers between QSPI devices and the FPGAs' Active Serial pins, as this can present propagation delay-induced timing issues, which may lead to configuration failures. A direct point-to-point connection between devices is recommended.

Stratix® 10 FPGAs and Agilex™ FPGAs series devices

Devices in this category employ a Triple Redundant Processor-based architecture (SDM) for configuration control and processing with dedicated SDM I/O pins that function based on user-defined settings. Below is a list of common mistakes made with these device families that could result in configuration failure.

Missing clocks during configuration

For designs that use transceivers, HBM2, PCIe, eSRAM, or HPS EMIF, the reference clocks for these must be stable and free running before configuration to avoid configuration failures. If a configuration with a simple design without such elements is successful, this indicates that a missing reference clock is causing configuration failure with the complete design.

• See Why does the configuration of Stratix® 10 FPGA devices fail when PCIe, HPS EMIF, eSRAM, or HBM2 IP is used in the Quartus® Prime Pro design?

SDM_IO pin connections do not match the Quartus® software project

SDM_IO functionality depends upon the user-defined Quartus® Prime project settings under Device & Pin Options -> Configuration -> Configuration Pins. Make sure these settings correlate with your board-level implementation.

nSTATUS is not monitored

It is recommended that the nSTATUS signal from the FPGA be monitored when controlling nCONFIG. This ensures a reconfiguration request is successful, as nCONFIG must only change when it has the same value as nSTATUS.  

• See Is there a minimum specification for how long nCONFIG should be driven low for successful configuration when using Stratix® 10 FPGAs and Agilex™ FPGA devices?

3V Tiles unpowered

Since designs that use 3V I/O are implemented on Transceiver Tiles, failure to power the respective transceiver tiles before configuration begins can result in configuration failure.

• See Why does Quartus® Programmer fail to configure Stratix® 10 FPGA devices when you are using 3V I/O pins?

Conflicting pull-up/downs on SDM_IO Pins

It is important to note that whilst most SDM_IO pins are weakly pulled high internally, some are weakly pulled low.

Mismatch between Configuration Clock source setting & board connection

The source for the internal oscillator can be set in the Quartus® Prime project. If OSC_CLK_1 is selected as the source, ensure the frequency setting matches what is equipped on the board. Note that if using Transceivers, a connection on OSC_CLK_1 is mandatory as this clock is used for Transceiver calibration. OSC_CLK_1 should be free-running throughout user mode.

See:

• Why do ASx4 configuration fail when using OSC_CLK_1 as clock source?
• Can I use the Internal Oscillator setting of the Configuration Clock Source field for transceiver calibration on Stratix® 10 FPGA L-Tile and H-Tile devices?
• Is OSC_CLK_1 required after configuration is successful?

Missing Reset Release IP in design

To ensure successful entry into user mode, it is recommended that you instance the Reset Release IP in your design to hold user logic in reset until device configuration and initialization are complete.

Conflicting MSEL connections/Debug provisioning

Since MSEL pins may drive out during power-up, Altera recommends only connecting a 4.7-kΩ pull-up or pull-down resistor to these pins and not driving them with active logic. It is also recommended that the MSEL pins be configured in JTAG mode for debug purposes.

Incorrect PMBus settings or usage of unsupported Voltage Regulators

When using SmartVID-enabled devices, please make sure the Quartus® Prime project settings correctly reflect the voltage regulator being used and that the Voltage Regulator uses a supported voltage output format as described in the Power Management User Guide for your chosen device. You must also ensure the voltage regulator's NVM is set correctly to ensure a successful configuration.

See:

• Is the PWRMGT_ALERT signal generated by the Stratix® 10 FPGA devices active high or active low?
• Are the Stratix® 10 FPGA device SDM_IO pins configured as open drain when used as PWRMGT_SDA and PWRMGT_SCL for SmartVID PMBus Power Management?
• Why do I need to ensure that all Stratix® 10 SmartVID devices use a PMBus voltage regulator?
• Guidelines: Selecting the Right Voltage Regulator

General (Applicable to all device families) 

Usage of unsupported 3rd-party SPI/QSPI devices for Active Serial Configuration

Altera recommends using one of the supported 3rd party QSPI flash devices for Active Serial configuration, where possible.

• See Supported Flash Memory Devices

10-Pin download cable header not connected correctly

The 10-pin download cable has a specific pin-out for Altera download cable headers, which should be followed to ensure compatibility with these cables.

Excessive load or signal integrity/timing issues on configuration interfaces/pins

Altera recommends simulating configuration topologies with IBIS models to verify signal integrity.

You may want to reduce the download cable speed (if supported) from 24 MHz, particularly if another device in the JTAG chain has a maximum supported TCK frequency of less than 24 MHz.

If multiple devices are connected in a JTAG chain, follow the buffering guidance in the following link:

• When should I buffer or terminate signals on a Joint Test Action Group (JTAG) chain?

Useful Reference

Device Configuration - Support Center

AN 955: Programmer’s Configuration Debugger Tool