Device Configuration - Support Center

Welcome to the Device Configuration Support Center!

Here you will find information on how to select, design, and implement configuration schemes and features. There are also guidelines on how to bring up your system and debug the configuration links. This page is organized into categories that align with a configuration system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Agilex™Intel® Stratix® 10Intel® Arria® 10, and Intel® Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation ArchiveTraining CoursesVideos and WebcastsDesign Examples, and Knowledge Base.

Table 1 - Configuration Schemes and Features Overview

Device Family Configuration Schemes Configuration Features
Scheme Data Width Max Clock Rate (1) Max Data Rate (1) Design Security Partial Reconfiguration (3) Remote System Update  Single Event Upsets Configuration via Protocol
Intel® Agilex Avalon®-ST 32 bits 125 MHz 4000 Mbps Parallel Flash Loader II IP core
16 bits 125 MHz 2000 Mbps
8 bits 125 MHz 1000 Mbps
Active Serial (AS) 4 bits 133(2) MHz 532 Mbps  √
SD/MMC 8 bits 50 MHz 400 Mbps N/A 
JTAG 1 bit 30 MHz 30 Mbps N/A N/A 
Intel® Stratix®  10 Avalon®-ST 32 bits 125 MHz 4000 Mbps Parallel Flash Loader II IP core
16 bits 125 MHz 2000 Mbps
8 bits 125 MHz 1000 Mbps
Active Serial (AS) 4 bits 133(2) MHz 532 Mbps  √
SD/MMC 8 bits 50 MHz 400 Mbps N/A 
JTAG 1 bit 30 MHz 30 Mbps N/A N/A 
Intel® Arria®  10 Configuration via HPS 32 bits 100 MHz 3200 Mbps via HPS  N/A 
16 bits 100 Mhz 1600 Mbps 
Fast Passive Parallel (FPP) 32 bits 100 MHz 3200 Mbps Parallel Flash Loader IP core N/A 
16 bits 100 Mhz 1600 Mbps
8 bits 100 Mhz  800 Mbps 
Active Serial (AS) 4 bits 100 MHz 400 Mbps (4)
1 bit 100 Mhz 100 Mbps
Passive Serial (PS) 1 bit 100 MHz 100 Mbps (4) Parallel Flash Loader IP core N/A 
JTAG 1 bit 33 MHz 33 Mbps   (4) N/A N/A 
Intel® Cyclone®  10 GX Fast Passive Parallel (FPP) 32 bits 100 MHz 3200 Mbps Parallel Flash Loader IP core N/A 
16 bits 100 Mhz 1600 Mbps
8 bits 100 Mhz  800 Mbps 
Active Serial (AS) 4 bit 100 MHz 400 Mbps (4)
1 bits 100 Mhz 100 Mbps
Passive Serial (PS) 1 bit 100 MHz 100 Mbps (4) Parallel Flash Loader  IP core N/A 
JTAG 1 bit 33 MHz 33 Mbps N/A  (4) N/A N/A 
Intel® Cyclone® 10 LP Fast Passive Parallel (FPP) 8 bits 66(5)/100(7) MHz 528(5)/800(7) Mbps N/A  N/A  Parallel Flash Loader  IP core N/A 
Passive Serial (PS) 1 bit 66(5)/133(6) MHz 66(5)/133(6) Mbps N/A  N/A  Parallel Flash Loader IP core N/A 
Active Serial (AS) 1 bit 40 MHz 40 Mbps N/A  N/A  N/A 
JTAG 1 bit 25 MHz 25 Mbps N/A  N/A  N/A N/A 
  1. The maximum clock rate and maximum data rate are preliminary.
  2. The maximum clock rate when using an external configuration clock source is 133 MHz. The maximum clock rate reduces if you use the internal oscillator as the configuration clock source, during SmartVID operation, or when the device is in user mode.
  3. You can perform partial reconfiguration after the device is fully configured. For more information, refer to the Partial Reconfiguration User Guide.
  4. Partial configuration can be performed only when it is configured as internal host.
  5. Supply voltage for internal logic, VCCINT = 1.0 V
  6. Supply voltage for internal logic, VCCINT = 1.2 V
  7. Supply voltage for internal logic, VCCINT = 1.2 V. Cyclone 10 LP 1.2 V core voltage devices support 133 MHz DCLK fMAX for 10CL006, 10CL010, 10CL016, 10CL025, and 10CL040 only.

Configure the FPGA portion of the SoC device by utilizing Hard Processor System (HPS)

Intel® Agilex Devices

Intel® Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Agilex™ Devices

Intel® Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Table 2 - Device Configuration Setting and Programming Files Generation Flow

1. General Setting
  •  General page of the Device and Pin Options dialog box in the Intel®  Quartus®  Prime Software.
  • Specify the device options. These options are independent on the configuration scheme.
2. Configuration Setting
 
  • Configuration page of the Device and Pin Options dialog box in the Intel®  Quartus®  Prime Software.
  • Specify the Device Configuration scheme, Configuration Device setting and Configuration Pin setting.
3. Programming Files Setting
  •  Programming Files page of the Device and Pin Options dialog box in the Intel®  Quartus®  Prime Software.
  •  Select the programming file format to generate. Selecting the programming file in this page is optional, user is recommended to use the Convert Programming File or Programming File Generator to convert/generate the type of programming file for the used of selected configuration scheme.
4. Others Optional Advanced Feature Setting
  • Error Detection CRC, CvP Settings and Partial Reconfiguration page of the Device and Pin Options dialog box in the Intel®  Quartus®  Prime Software.
  • Error Detection CRC page - Specify whether error detection is used and the rate at which it is checked.
  • CvP Settings page - Specify the type of CvP settings
  • Partial Reconfiguration page - Specify Partial Reconfiguration settings
5. Generate Configuration and Programming Files
  • Once design compilation is completed, the Convert Programming Files or Programming File Generator is the tool in Intel®  Quartus®  Prime Software to convert/generate the type of programming file for selected configuration scheme or configuration feature.

Intel® Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Intel® Cyclone® 10 LP Devices

The configuration specification in the device datasheet specifies the following specifications:

  • Timing specifications for configuration control pins
  • Timing/Performance specifications for each of the supported configuration scheme
  • Configuration bit stream sizes
  • Configuration time estimation for each of the supported configuration scheme

Intel® Agilex Devices

Intel® Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Intel® Cyclone® 10 LP Devices

Intel Stratix® 10 FPGA SDM Debug Toolkit helps you debug your configuration issues.
  • It is available in Intel® Quartus® Prime Pro Edition software v18.1 and onwards.

Searching a tool to debug configuration failures / design security / error detection cyclic redundancy check (CRC) on Intel® Arria® 10 devices? 

  • To get this configuration diagnostic tool, please contact your Intel® sales representative.
You can use this troubleshooter or fault tree analysis to identify possible configuration failure causes.

Go to Knowledge Base, enter the keywords of the issue you face to find for the solution. 

Table 3 shows the criteria of third party configuration devices supported by Intel® Quartus® Convert Programming File Tools and Quartus® Programmer version 18.1 Standard and Pro Edition. 

Table 3 - Intel Supported Third Party Configuration Devices

Intel® FPGA Vendor P/N Byte addressing Dummy Clock Settings Permanent Quad-Enabled flash? Intel® Tested and Supported Flash Devices
ASx1 ASx4
Intel® Stratix® 10 Micron*  MT25QU128 3-byte(1) 8(4) 10(4) No(6) MT25QU128ABA8ESF-0SIT
MT25QU256 MT25QU256ABA8E12-1SIT
MT25QU512 MT25QU512ABB8ESF-0SIT
MT25QU01G MT25QU01GBBB8ESF-0SIT
MT25QU02G MT25QU02GCBB8E12-0SIT
Macronix* MX25U128(10) 3-byte(1) 8(1) 6(1) No(6) MX25U12835FMI-100
MX25U256(10) MX25U25645GMI00
MX25U512(10) MX25U51245GMI00
MX66U512(10) MX66U51235FXDI-10G
MX66U1G(10) MX66U1G45GXDI00
MX66U2G(10) MX66U2G45GXRI00
Intel® Arria® 10, Intel® Cyclone® 10 GX Micron* MT25QU256 4-byte(4) 10(4) 10(4) No(6) MT25QU256ABA8E12-1SIT
MT25QU512 MT25QU512ABB8ESF-0SIT
MT25QU01G MT25QU01GBBB8ESF-0SIT
MT25QU02G MT25QU02GCBB8E12-0SIT
Macronix* MX25U256(3) 4-byte(5) 10(5) 10(5) Yes(6) MX25U25645GXDI54
MX25U512(3) MX25U51245GXDI54
MX66U1G(3) MX66U1G45GXDI54
MX66U2G(3) MX66U2G45GXRI54
Cyclone® V, Arria® V, Stratix® V Micron* MT25QL128 3-byte(1) 12(4) 12(4) No(6) MT25QL128ABA8ESF-0SIT
MT25QL256 4-byte(4) 4(4) 10(4) No(6) MT25QL256ABA8ESF-0SIT
MT25QL512 MT25QL512ABB8ESF-0SIT
MT25QL01G MT25QL01GBBB8ESF-0SIT
MT25QL02G MT25QL02GCBB8E12-0SIT
Macronix* MX25L128 3-byte(1)(2) 8(1) 6(1) No(6) MX25L12833FMI-10G
MX25L256 MX25L25645GMI-08G
MX25L512 MX25L51245GMI-08G
Cypress* S25FL128 3-byte(1)(2) 8(1) 7(1) No(6) S25FL128SAGMFI000
S25FL256 S25FL256SAGMFI000
S25FL512 S25FL512SAGMFI0I0
Cyclone® 10 LP Micron* MT25QL128 3-byte(1)(2) 8(1) N/A  No(6) MT25QL128ABA8ESF-0SIT
MT25QL256 MT25QL256ABA8ESF-0SIT
MT25QL512 MT25QL512ABB8ESF-0SIT
MT25QL01G MT25QL01GBBB8ESF-0SIT
MT25QL02G MT25QL02GCBB8E12-0SIT
Macronix* MX25L128 3-byte(1)(2) 8(1) N/A  No(6) MX25L12833FMI-10G
MX25L256 MX25L25645GMI-08G
MX25L512 MX25L51245GMI-08G
Cypress* S25FL128 3-byte(1)(2) 8(1) N/A  No(6) S25FL128SAGMFI000
S25FL256 S25FL256SAGMFI000
S25FL512 S25FL512SAGMFI0I0
  1. Using the default setting of the configuration devices.
  2. When performing remote system upgrade, the start address of the images must be set within first 128 Mb.
  3. Intel® Arria® 10 and Intel® Cyclone® 10 GX supports only Macronix* configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54, MX66U2G45GXRI54.
  4. Intel® Quartus® Progammer set the non-volatile configuration register during programming operation. User need to set the register manually if using a third party programmer.
  5. The configuration devices is permanent to this value, user do not have the options to change this setting.    
  6. Intel® Quartus® Programmer issues command to enable quad mode   
  7. These configuration devices are not supported by legacy ASMI Parallel I Intel® FPGA IP core and ASMI Parallel II Intel® FPGA IP core. For new design, please refer to Generic Serial Flash Interface Intel® FPGA IP core.
  8. AS x 1 - Active serial configuration support 1 bit data width
  9. AS x 4 - Active serial configuration scheme support 4 bit data width
  10. Intel® Stratix® 10 doesn't support Macronix* configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54 and MX66U2G45GXRI54.
Title  Type Description
Introduction to Configuring Intel® FPGAs Online Learn the configuration schemes, solutions, features and tools available for configuring Intel® FPGAs and programming configuration devices.
Configuration Schemes for Intel® FPGAs Online Learn the difference between all the configuration schemes that can be used to configure Intel® FPGAs.
Configuration Solutions for Intel FPGAs Online Learn about the Intel® FPGAs configuration devices, serial and parallel flash loaders and the embedded configuration solutions
Configuration for Intel®  Stratix® 10 Devices Online Learn the unique configuration features available in the Intel® Stratix® 10 devices
Remote System Upgrade in Intel® MAX® 10 Devices Online Learn how to set up and perform a RSU in an Intel MAX 10 device
Creating Second Stage Bootloader for Altera SoCs Online  Learn the flow and tools available to quickly customize and generate the second stage boot software
Secure Boot with Intel® Arria® 10 SoC FPGAs Online Learn to generate and program Intel® Arria® 10 SoC FPGAs with and encrypted and/or signed second stage boot image
Mitigating Single Event Upsets in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices  Online  Learn the features of the  Intel® Arria® 10 and Intel® Cyclone® 10 GX device families that can be used in the designing your own SEU mitigation solution
SEU Mitigation in Intel® FPGA Devices: Hierarchy Tagging Online Learn how you can improve your sensitivity processing solution by supplementing single event upset (SEU) mitigation technique with feature called hierarchy tagging
SEU Mitigation in Intel® FPGA Devices: Fault Injection Online Learn about Fault Injection IP core and Fault Injection Debugger software to reduce Failure in Time (FIT) rate
Using the Generic Serial Flash Interface Online  Learn how to use the Generic Serial Flash Interface Intel FPGA IP Core to program any serial peripheral interface (SPI) type flash device 
Title  Description
Configuration via Protocol (CvP) Watch this video to learn how to configure your Intel® Arria® 10 device using the PCIe* protocol.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part1 Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part2 Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Perform Active Serial (AS) Configuration via JTAG Interface Using Serial Flash Loader IP Core   Watch this video to learn about configuration schemes other than the usual JTAG configuration. Additionally, this video covers the serial flash loader (SFL) IP core.

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