1.4. Guidelines: Selecting the Right Voltage Regulator
All SmartVID devices must be driven by the PMBus-compliant voltage regulator, operating either in the master mode or slave mode. Intel® recommends you to use one of the slave device type listed in the drop-down menu in the Quartus® Prime software that has been tested with the Intel® FPGA tools.
Figure 1. Stratix® 10 and Agilex™ Voltage Regulator Selection
You can use voltage regulator that are not listed in the GUI by selecting the "Other" option in the Quartus® Prime software. To choose other voltage regulator, you must ensure the voltage regulator is PMBus-compliant and compatible with the Intel® firmware.
Attention: You must ensure that the NVM of the voltage regulator is set correctly. This is to ensure a successful configuration.
NVM Setting of the Voltage Regulator for the Stratix® 10 Device
VOUT_OV_WARN_LIMIT to VID_MAX 920mV
VOUT_OV_FAULT_LIMIT to VID_MAX 930mV
VOUT_MAX to VID_MAX 950mV
VOUT_UV_WARN_LIMIT to VID_MIN 790mV
VOUT_UV_FAULT_LIMIT to VID_MIN 770mV
NVM Setting of the Voltage Regulator for the Agilex™ 7 Device
VOUT_OV_WARN_LIMIT to VID_MAX 927mV
VOUT_OV_FAULT_LIMIT to VID_MAX 930mV
VOUT_MAX to VID_MAX 950mV
VOUT_UV_WARN_LIMIT to VID_MIN 690mV
VOUT_UV_FAULT_LIMIT to VID_MIN 680mV
NVM Setting of the Voltage Regulator for the Agilex™ 5 Device
VOUT_OV_WARN_LIMIT to VID_MAX 927mV
VOUT_OV_FAULT_LIMIT to VID_MAX 930mV
VOUT_MAX to VID_MAX 950mV
VOUT_UV_WARN_LIMIT to VID_MIN 690mV
VOUT_UV_FAULT_LIMIT to VID_MIN 680mV
Limit should be wider or larger than the expected operating conditions, but within the absolute maximum rating for the device. For more information, refer to your selected device data sheet.
The VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT are based on the Recommended Operating Condition table, while the VOUT_OV_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT are based on the Absolute Maximum Ratings table in your selected device data sheet.
Note: The safety limit registers do not exist on all voltage regulators. You must consult the voltage regulator vendor for guidance to configure your voltage regulator to support the FPGA's voltage requirements.
| Number | Done? | Requirement | Checklist Item | Notes |
|---|---|---|---|---|
| 1 | Must | PMBus-compliant | The chosen voltage regulator must be a 1.3 PMBus-compliant device. | |
| 2 | Must | PMBus commands | The chosen voltage regulator can be operated without requiring any vendor-specific command. All commands must be:
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| 3 | Must | Configurable | The chosen voltage regulator has a configurable power-on voltage that aligns with the FPGA's data sheet specifications. Do not require the power management firmware (PMF) to turn it on. The voltage regulator must power up on its own.
Note: The voltage regulator must power up first before starting configuration.
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| 4 | Must | Noise-resistant and error resetting | The voltage regulator's I2C interface must be resistant to noise1. The voltage regulator firmware must be able to detect noise on the bus and reset without intervention. Have a message timeout value in the event an incomplete message is received. On timeout, the voltage regulator must flush its input or output buffers and reset the I2C interface. |
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| 5 | Must | Operation mode | The voltage regulator must be able to operate in either the direct or linear mode. | |
| 6 | Must | Bit address | Supports the 7-bit address. | |
| 7 | Must | Bus speed | Supports 100 kHz and 400 kHz. | |
| 8 | Must | Threshold setting | Configurable over voltage or current. Configurable under voltage or current. | |
| 9 | Optional | Multi-master compatibility | Multi-master mode compatible. | |
| 10 | Optional | Analog-to-digital converter (ADC) sampling rate | The ADC sampling data rate of less than 10 ms without requiring additional command.
Note: If the sampling data rate is more than 10 ms, it can cause configuration error.
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| 11 | Recommended | Direct PMBus connection between the secure device manager (SDM) and voltage regulator | To avoid any communication error, Intel® recommends you to set the direct connection and communication between the SDM (FPGA) with the voltage regulator. |
Attention: For the list of application programming interface (API)-validated voltage regulator, refer to the Intel® FPGA SmartVID page. The API-validated voltage regulators' functionality are confirmed and compatible with the Intel® FPGA and power management firmware.
| Number | Done? | PMBus Command | Purpose | Description | Requirement | |
|---|---|---|---|---|---|---|
| Master | Slave | |||||
| 1 | PAGE(00h) | Selects the set of voltage regulator control registers | This is only required if the voltage regulator has multiple sets of control registers. | Optional2 | — | |
| 2 | VOUT_COMMAND(21h) | Sets the voltage | Sets the voltage using either the linear or direct mode format. This command must not be password protected or require command sequences to send.
Attention: This command must use the same encoding or decoding as the READ_VOUT. You must ensure that the voltage regulator has the same resolution as the VOUT or READ_VOUT.
3 |
Required | Required | |
| 3 | READ_VOUT(8Bh) | Returns the voltage regulator's output voltage | Returns the voltage regulator voltage using either the linear or direct mode format.
Attention: This command must use the same encoding or decoding as the VOUT_COMMAND. The voltage regulator must be able to respond to multiple continuous READ_VOUT commands.
3 |
Required | — | |
| 4 | VOUT_MODE(20h) | Returns the mode the voltage regulator uses to report voltage | Retrieves the voltage regulator supported VOUT format using either the linear format or direct format. | Required | Required | |
| 5 | STATUS_BYTE(78h) | Returns the voltage regulator status | This command returns one byte of data that indicates the current status of the voltage regulator. For the status byte error message, refer to the respective Power Management User Guide. | Required | Required | |
| 6 | CLEAR_FAULTS(03h) | Clears any voltage regulator faults | This command clears any fault bits that have been set. | Required | Required | |
1 Noise can be misinterpreted as commands.
2 Required for multiple rails voltage regulator.
3
You are required to use the voltage regulator with the same encoding and decoding between the READ_VOUT and VOUT_COMMAND. If both the READ_VOUT and VOUT_COMMAND are not in the same resolution, it causes the PMBus communication error during voltage update.
The MPM voltage regulator has different encoding and decoding for the READ_VOUT and VOUT_COMMAND. For the list of API-validated voltage regulator, refer to the Intel® FPGA SmartVID page.