1.4.1. Schematic Design Example
Level shifter is a circuitry that is used to translate the signal level from 1.8 V to 3.3 V.
Note: The SDM limit is 1.8 V I/O standard. To ensure correct PMBus operation between the SDM and other PMBus components, you must adhere to this limit.
There are two types of level-shifter design:
- A non-buffered level shifter—passes the capacitive load from the whole I2C bus, making the clock or data edges more sloped and causes the PMBus communication issues.
- A buffered level shifter—does not pass the capacitive load, making the clock or data edges less sloped (cleaner) and avoids the PMBus communication issues.
Note: To avoid issue during the PMBus communication, Intel® recommends implementing the buffered level shifter for the PMBus.
The following figure is the schematic design example for the level shifter.
Figure 2. Schematic Design Example—Level Shifter
The voltage regulator module (VRM) must be designed based on your selected voltage regulator. To avoid any issue, refer to your selected device data sheet for the detailed requirements.
The following are the schematic design examples of the voltage regulator power modules for the seven phases.
Figure 3. Schematic Design Example—Port Connection
Figure 4. Schematic Design Example—V CC Core Power
Figure 5. Schematic Design Example—Power Phases 0 and 1
Figure 6. Schematic Design Example—Power Phases 2 and 3
Figure 7. Schematic Design Example—Power Phases 4, 5, and 6