SmartVID Debug Checklist and Voltage Regulator Guidelines

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ID 757318
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. SmartVID Debug Checklist and Voltage Regulator Guidelines
1. SmartVID Debug Checklist and Voltage Regulator Guidelines x
1.1. SmartVID-related Subcode Error Messages for Agilex™ Devices Only 1.2. Description of Subcode Error Messages for Agilex™ Devices Only 1.3. PMBus Master and Slave Modes Checklist 1.4. Guidelines: Selecting the Right Voltage Regulator 1.5. Steps to Obtain the Voltage Output Information from the Voltage Regulator Data Sheet 1.6. Steps to Decode the PMBus Transaction Log 1.7. Document Revision History for the SmartVID Debug Checklist and Voltage Regulator Guidelines
1.3. PMBus Master and Slave Modes Checklist x
1.3.1. PMBus Master Mode Checklist 1.3.2. PMBus Slave Mode Checklist
1.4. Guidelines: Selecting the Right Voltage Regulator x
1.4.1. Schematic Design Example
1. SmartVID Debug Checklist and Voltage Regulator Guidelines

1.3.2. PMBus Slave Mode Checklist

Table 3.  PMBus Slave Mode Checklist
Number Done? Checklist Item Notes
1   Assign the correct pin assignment for PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT in the Quartus® Prime software.
  • Ensure the pin assignment for PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT are assigned correctly in the Quartus® Prime > Device > Device and Pin Options > Configuration > Configuration Pin Options.
  • Incorrect pin assignment for these pins causes configuration error due to invalid PMBus interface connection on the hardware or board.
2  

Set the correct VID parameters in the Quartus® Prime software:

  • Device address in the PMBus slave mode
  • Ensure the VID parameters are set correctly in the Quartus® Prime > Device > Device and Pin Options > Power Management and VID.
  • Incorrect VID parameters cause configuration error due to PMBus interface communication error.
  • Device address is always in hexadecimal format.
3  

For the PMBus on-board connection:

  • Connect the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT pins to pull-up resistor.
  • Bi-directional level shifter between the FPGA and the external voltage regulator.
  • For the connection guidelines, refer to the respective Pin Connection Guidelines.
  • Connect the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT pins to a 1.8 V pull-up resistor.
  • Ensure level shifter is placed on board between the FPGA PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT pins and the external voltage regulator.
  • In general, the PMBus operates with 3.3 V single-ended I/O standard. Due to the limitation on FPGA that supports only 1.8 V single-ended I/O standard, a 1.8 V – 3.3 V level shifter is required to transfer or receive data from the external voltage regulator.
4  

The external voltage regulator must be PMBus-compliance:

  • Intel® recommends using the voltage regulator under the Intel® validated list.
  • If you are unable to select one of the Intel® validated regulators, refer to the Voltage Regulator Compatibility Check with the Intel® Power Management Firmware table to check the compatibility your selected voltage regulator with the Intel® 's firmware.
  • Specified command is required to ensure the FPGA's SmartVID firmware is able to successfully communicate with the external voltage regulator.
5  

Configuration failure can happen during the first-time configuration after power up, or during configuration.

  • If the configuration failure happens during reconfiguration, power cycle the device.
  • Direct JTAG configuration.
  • If the SmartVID failed to detect the VOUT_COMMAND within 200 ms after the PWRMGT_ALERT is asserted, the device fails configuration.
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