Article ID: 000075330 Content Type: Troubleshooting Last Reviewed: 03/07/2023

Why does the configuration of Intel® Stratix® 10 devices fail when PCIe, HPS EMIF, eSRAM, or HBM2 IP is used in the Intel® Quartus® Prime Pro Edition Software design?


  • Intel® Quartus® Prime Pro Edition
  • Generic Component

    Intel® Stratix® 10 devices have additional clock requirements for successful configuration when Hard Processor System External Memory Interface (HPS EMIF), PCIe, eSRAM, or High Bandwidth Memory (HBM2) is used.

    The reference clocks are required for proper PLL calibration to ensure the aforementioned IP blocks can function properly when the device has completed configuration and entered user mode. The Secure Device Manager (SDM) firmware gates the device configuration if the PLL is not calibrated properly due to a missing reference clock. Thus, users must provide a free-running, stable reference clock to these IP blocks before configuration begins. The required reference clock for the respective IP is stated below: 

    IPClock Pin
    HBM2pll_ref_clk and ext_core_clk
    eSRAMCLK_ESRAM_[0,1]p and CLK_ESRAM_[0,1]n
    HPS EMIFpll_ref_clk
    L- and H-Tile PCIe ChannelsREFCLK_GXB
    E-Tile Transceivers ChannelsREFCLK_GXE


    For Intel® Stratix® 10 L/H-tile devices, the reference clock requirement is mandatory for PCIe use cases but not mandatory for non-PCIe use cases for a successful device configuration. For the PCIe use case, the SDM firmware will wait for the PLL calibration code to ensure the PLL is calibrated properly to release the device for entering user mode. Therefore, a reference clock is mandatory for PLL calibration. For non-PCIe use cases, SDM firmware will not gate device configuration without a proper PLL calibration code without reference clock supply during configuration. Users can calibrate the transceiver PLL in user mode for transceiver channels to operate properly.

    For Intel® Stratix® 10 E-tile devices, the reference clock requirement is mandatory for successful device configuration. The reference clock is required to load the configuration firmware into Intel® Stratix® 10 E-tile devices.


    Ensure you provide a free-running, stable reference clock to the transceiver, PCIe, HPS EMIF, eSRAM, and HBM2 IP blocks if they are being used in your design before configuration begins.



    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs