System Console is a flexible system-level debugging tool that helps designers quickly and efficiently debug their design while the design is running at full speed in an FPGA. System Console enables designers to send read and write system-level transactions into their Platform Designer (formerly Qsys) system to help isolate and identify problems. It also provides a quick and easy way to check system clocks and monitor reset states, which can be particularly helpful during board bring-up. In addition, System Console allows designers to create their own custom verification or demonstration tool using graphical elements, such as buttons, dials, and graphs, to represent many system-level transactions and monitor the processing of data.
System Console can also be integrated with MATLAB* and Simulink* for System in the Loop functionality. For more information, visit the FPGA Verification in MATLAB* Environment page.
- Read the System-Level Debugging and Monitoring of FPGA Designs (PDF) white paper
- Watch the System Console video demos
- Faster Board Bring-Up with System Console ›
- Building a Custom Verification GUI with System Console ›
- Download the Qsys System Design Tutorial (PDF) (includes System Console)
- Read the Verification (PDF) handbook chapter
- Take a System Console training class
- Free online training – System Console ›
- Instructor-led training – Introduction to the Qsys System Integration Tool ›
- Learn about other applications developed on System Console
- Transceiver Toolkit ›
- UniPHY External Memory Interface Debug Toolkit (PDF) handbook chapter