22.214.171.124. Outputs from the FPGA to the LPDDR2 Component
The following output signals are from the FPGA to the LPDDR2 SDRAM component:
- write data (DQ)
- data mask (DM)
- data strobe (DQS/DQS#)
- command address
- command (CS, and CKE)
- clocks (CK/CK#)
No far-end memory termination is needed when driving output signals from FPGA to LPDDR2 SDRAM. Cyclone V and Arria V devices offer the OCT series termination for impedance matching.
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