External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Public
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4.1.2.1. Outputs from the FPGA to the LPDDR2 Component

The following output signals are from the FPGA to the LPDDR2 SDRAM component:

  • write data (DQ)
  • data mask (DM)
  • data strobe (DQS/DQS#)
  • command address
  • command (CS, and CKE)
  • clocks (CK/CK#)

No far-end memory termination is needed when driving output signals from FPGA to LPDDR2 SDRAM. Cyclone V and Arria V devices offer the OCT series termination for impedance matching.