10.1.1. Dedicated IOE DQS Group Resources and Pins
Such a constraint requires that the chosen device meets the following conditions:
- Sufficient DQS groups and sizes to support the required number of common I/O (CIO) or separate I/O (SIO) data groups.
- Sufficient remaining pins to support the required number of address, command, and control pins.
Failure to evaluate these fundamental requirements can result in suboptimal interface design, if the chosen device cannot be modified. The resulting wraparound interfaces or suboptimal pseudo read and write data groups artificially limit the maximum operating frequency.
Multiple blocks of IP further complicate the issue, if other IP has either no specified location constraints or incompatible location constraints.
The Quartus Prime fitter may first place other components in a location required by your memory IP, then error at a later stage because of an I/O assignment conflict between the unconstrained IP and the constrained memory IP.
Your design may require that one instance of IP is placed anywhere on one side of the device, and that another instance of IP is placed at a specific location on the same side.
While the two individual instances may compile in isolation, and the physical number of pins may appear sufficient for both instances, issues can occur if the instance without placement constraints is placed before the instance with placement constraints.
In such circumstances, Intel® recommends manually placing each individual pin, or at least try using more granular placement constraints.
For more information about the pin number and DQS group capabilities of your chosen device, refer to device data sheets or the Quartus Prime Pin Planner.
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