External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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2.1.3.2. FPGA Reading from Memory

The following figure shows the dynamic parallel termination scheme when the FPGA is reading from memory.

When the SDRAM DIMM is driving the transmission line, the ringing and reflection is minimal because the FPGA-side termination 50-ohm pull-up resistor is matched with the transmission line.

Figure 14. Dynamic Parallel OCT Scheme with Memory-Side Series Resistor