External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.1.20. OCT Support

If the memory interface uses any FPGA OCT calibrated series, parallel, or dynamic termination for any I/O in your design, you need a calibration block for the OCT circuitry. This calibration block is not required to be within the same bank or side of the device as the memory interface pins. However, the block requires a pair of RUP and RDN or RZQ pins that must be placed within an I/O bank that has the same VCCIO voltage as the VCCIO voltage of the I/O pins that use the OCT calibration block.

The RZQ pin in Arria 10, Stratix 10, Arria V, Stratix V, and Cyclone V devices can be used as a general purpose I/O pin when it is not used to support OCT, provided the signal conforms to the bank voltage requirements.

The RUP and RDN pins in Arria II GX, Arria II GZ, MAX 10, Stratix III, and Stratix IV devices are dual functional pins that can also be used as DQ and DQS pins in when they are not used to support OCT, giving the following impacts on your DQS groups:

  • If the RUP and RDN pins are part of a ×4 DQS group, you cannot use that DQS group in ×4 mode.
  • If the RUP and RDN pins are part of a ×8 DQS group, you can only use this group in ×8 mode if any of the following conditions apply:
    • You are not using DM or BWSn pins.
    • You are not using a ×8 or ×9 QDR II SRAM device, as the RUP and RDN pins may have dual purpose function as the CQn pins. In this case, pick different pin locations for RUP and RDN pins, to avoid conflict with memory interface pin placement. You have the choice of placing the RUP and RDN pins in the same bank as the write data pin group or address and command pin group.
    • You are not using complementary or differential DQS pins.
Note: The Altera external memory interface IP does not support ×8 QDR II SRAM devices in the Quartus Prime software.

A DQS/DQ ×8/×9 group in Arria II GZ, Stratix III, and Stratix IV devices comprises 12 pins. A typical ×8 memory interface consists of one DQS, one DM, and eight DQ pins which add up to 10 pins. If you choose your pin assignment carefully, you can use the two extra pins for RUP and RDN . However, if you are using differential DQS, you do not have enough pins for RUP and RDN as you only have one pin leftover. In this case, as you do not have to put the OCT calibration block with the DQS or DQ pins, you can pick different locations for the RUP and RDN pins. As an example, you can place it in the I/O bank that contains the address and command pins, as this I/O bank has the same VCCIO voltage as the I/O bank containing the DQS and DQ pins.

There is no restriction when using ×16/×18 or ×32/×36 DQS groups that include the ×4 groups when pin members are used as RUP and RDN pins, as there are enough extra pins that can be used as DQS or DQ pins.

You must pick your DQS and DQ pins manually for the ×8, ×9, ×16 and ×18, or ×32 and ×36 groups, if they are using RUP and RDN pins within the group. The Quartus Prime software might not place these pins optimally and might be unable to fit the design.

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